Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate.
Liao WangMasanori HashimotoPublished in: IEICE Trans. Electron. (2019)
Keyphrases
- error rate
- high speed
- equal error rate
- cmos technology
- test set
- low cost
- low power
- analog vlsi
- evolvable hardware
- logic circuits
- power consumption
- circuit design
- power dissipation
- random access memory
- lower error rates
- misclassification rate
- power reduction
- false discovery rate
- high density
- low voltage
- rejection rate
- cost sensitive classification
- asynchronous circuits
- training error
- digital circuits
- image sensor