Zhengya Zhang

ORCID

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 73

Top Venues

IEEE J. Solid State Circuits

ISSCC

VLSI Circuits

A-SSCC

Publications

Fan-Hsuan Meng, Yuting Wu, Zhengya Zhang, Wei D. Lu
TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (3) (2024)
Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, Youngjoo Lee
2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications. ISSCC (2024)
Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. IEEE J. Solid State Circuits 59 (4) (2024)
Jie-Fang Zhang, Cheng-Hsun Lu, Zhengya Zhang
TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing. IEEE Trans. Computers 73 (5) (2024)
Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang
AIB 2.0 Interface to Provide Versatile Workload Acceleration. VLSI Technology and Circuits (2023)
Junkang Zhu, Yaoyu Tao, Zhengya Zhang
eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs. HPCA (2023)
Teyuh Chou, Fernando García-Redondo, Paul N. Whatmough, Zhengya Zhang
AR-PIM: An Adaptive-Range Processing-in-Memory Architecture. ISLPED (2023)
Reid Pinkham, Jack Erhardt, Barbara De Salvo, Andrew Berkovich, Zhengya Zhang
ANSA: Adaptive Near-Sensor Architecture for Dynamic DNN Processing in Compact Form Factors. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (3) (2023)
Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes. CoRR (2022)
Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn
An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits (2022)
Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, Zhengya Zhang
VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters. IEEE J. Solid State Circuits 57 (11) (2022)
Xinxin Wang, Reid Pinkham, Mohammed Affan Zidan, Fan-Hsuan Meng, Michael P. Flynn, Zhengya Zhang, Wei D. Lu
TAICHI: A Tiled Architecture for In-Memory Computing and Heterogeneous Integration. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Teyuh Chou, Wei Tang, Mihai D. Rotaru, Chester Liu, Rahul Dutta, Sharon Lim Pei Siang, David Ho Soon Wee, Surya Bhattacharya, Zhengya Zhang
NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. VLSI Technology and Circuits (2022)
Yaoyu Tao, Zhengya Zhang
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer. CoRR (2022)
Chester Liu, Jacob Botimer, Zhengya Zhang
A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. CICC (2021)
Junkang Zhu, Wei Tang, Ching-En Lee, Haolei Ye, Eric McCreath, Zhengya Zhang
VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters. VLSI Circuits (2021)
Reid Pinkham, Andrew Berkovich, Zhengya Zhang
Near-Sensor Distributed DNN Processing for Augmented and Virtual Reality. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (4) (2021)
Jie-Fang Zhang, Zhengya Zhang
Point-X: A Spatial-Locality-Aware Architecture for Energy-Efficient Graph-Based Point-Cloud Deep Learning. MICRO (2021)
Yaoyu Tao, Zhengya Zhang
DNC-Aided SCL-Flip Decoding of Polar Codes. GLOBECOM (2021)
Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture. IEEE J. Solid State Circuits 56 (2) (2021)
Jie-Fang Zhang, Zhengya Zhang
Exploration of Energy-Efficient Architecture for Graph-Based Point-Cloud Deep Learning. SiPS (2021)
Yaoyu Tao, Zhengya Zhang
HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer. MICRO (2021)
Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System. IEEE J. Solid State Circuits 56 (6) (2021)
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. IEEE J. Solid State Circuits 56 (2) (2021)
Yaoyu Tao, Zhengya Zhang
DNC-Aided SCL-Flip Decoding of Polar Codes. CoRR (2021)
Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. VLSI Circuits (2021)
Zhengya Zhang, Anke Klingner, Sarthak Misra, Islam S. M. Khalil
Control of Magnetically-Driven Screws in a Viscoelastic Medium. IROS (2020)
Thomas Chen, Jacob Botimer, Teyuh Chou, Zhengya Zhang
56.9-GOPS Accelerator for Solving Partial Differential Equations. IEEE J. Solid State Circuits 55 (6) (2020)
Reid Pinkham, Shuqing Zeng, Zhengya Zhang
QuickNN: Memory and Performance Optimization of k-d Tree Based Nearest Neighbor Search for 3D Point Clouds. HPCA (2020)
Sung-Gun Cho, Edith Beigné, Zhengya Zhang
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. CICC (2019)
Teyuh Chou, Wei Tang, Jacob Botimer, Zhengya Zhang
CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. MICRO (2019)
Thomas Chen, Ching-En Lee, Chester Liu, Zhengya Zhang
A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification. IEEE J. Solid State Circuits 54 (7) (2019)
Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS. VLSI Circuits (2019)
Thomas Chen, Jacob Botimer, Teyuh Chou, Zhengya Zhang
An Sram-Based Accelerator for Solving Partial Differential Equations. CICC (2019)
Jie-Fang Zhang, Ching-En Lee, Chester Liu, Yakun Sophia Shao, Stephen W. Keckler, Zhengya Zhang
SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. VLSI Circuits (2019)
Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS. IEEE J. Solid State Circuits 54 (7) (2019)
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2019)
Chester Liu, Sung-Gun Cho, Zhengya Zhang
718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS. IEEE J. Solid State Circuits 53 (10) (2018)
Wei Tang, Hemanth Prabhu, Liang Liu, Viktor Öwall, Zhengya Zhang
A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. ISSCC (2018)
Mohammed Affan Zidan, YeonJoo Jeong, Jong Hoon Shin, Chao Du, Zhengya Zhang, Wei D. Lu
Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing. IEEE Trans. Multi Scale Comput. Syst. 4 (4) (2018)
Shiming Song, Kyojin David Choo, Thomas Chen, Sunmin Jang, Michael P. Flynn, Zhengya Zhang
A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2018)
Zhengya Zhang, Matilde Santos
Optimizing a Fuzzy Equivalent Sliding Mode Control Applied to Servo Drive Systems. SOCO-CISIS-ICEUTE (2018)
Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Luyao Gong, Zhengya Zhang, Ronald G. Dreslinski, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim
A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles. IEEE J. Solid State Circuits 53 (1) (2018)
Shiming Song, Wei Tang, Thomas Chen, Zhengya Zhang
140mW lattice encryption instruction accelerator in 40nm CMOS. CICC (2018)
Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou
A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. ESSCIRC (2018)
Chester Liu, Zhengya Zhang
Inference and Learning Hardware Architecture for Neuro- Inspired Sparse Coding Algoerithm. BioCAS (2018)
Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou
20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. ISSCC (2017)
Chester Liu, Sung-Gun Cho, Zhengya Zhang
718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. A-SSCC (2017)
John Bell, Phil Knag, Shuanghong Sun, Yong Lim, Thomas Chen, Jeffrey Fredenburg, Chia-Hsiang Chen, Chunyang Zhai, Aaron Z. Rocca, Nicholas Collins, Andres Tamez, Jorge Pernillo, Justin M. Correll, Alan B. Tanner, Zhengya Zhang, Michael P. Flynn
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging. IEEE J. Solid State Circuits 52 (5) (2017)
Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
AES core with DPA resistance for IoT devices. A-SSCC (2017)
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Ziyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Shijia Yang, Zhengya Zhang, Ronald G. Dreslinski, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim
3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation. ISSCC (2017)
Shuanghong Sun, Sung-Gun Cho, Zhengya Zhang
Post-Processing Methods for Improving Coding Gain in Belief Propagation Decoding of Polar Codes. GLOBECOM (2017)
Shuanghong Sun, Zhengya Zhang
Designing Practical Polar Codes Using Simulation-Based Bit Selection. IEEE J. Emerg. Sel. Topics Circuits Syst. 7 (4) (2017)
Haichang Gao, Jeff Yan, Fang Cao, Zhengya Zhang, Lei Lei, Mengyun Tang, Ping Zhang, Xin Zhou, Xuqin Wang, Jiawei Li
A Simple Generic Attack on Text Captchas. NDSS (2016)
Shuanghong Sun, Sung-Gun Cho, Zhengya Zhang
Error patterns in belief propagation decoding of polar codes and their mitigation methods. ACSSC (2016)
Shuanghong Sun, Zhengya Zhang
Architecture and optimization of high-throughput belief propagation decoding of polar codes. ISCAS (2016)
Phil Knag, Chester Liu, Zhengya Zhang
141mW 898GOPS sparse neuromorphic processor in 40nm CMOS. VLSI Circuits (2016)
Mohammed Affan Zidan, YeonJoo Jeong, Jong Hoon Shin, Chao Du, Zhengya Zhang, Wei D. Lu
Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing. CoRR (2016)
Todd Gaier, Pekka Kangaslahti, Bjorn Lambrigtsen, Isaac Ramos-Pérez, Alan B. Tanner, Darren McKague, Christopher Ruf, Michael J. Flynn, Zhengya Zhang, Roger Backhus, David Austerberry
A 180 GHz prototype for a geostationary microwave imager/sounder-GeoSTAR-III. IGARSS (2016)
Haichang Gao, Xuqin Wang, Fang Cao, Zhengya Zhang, Lei Lei, Jiao Qi, Xiyang Liu
Robustness of text-based completely automated public turing test to tell computers and humans apart. IET Inf. Secur. 10 (1) (2016)
Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang
3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication. J. Signal Process. Syst. 84 (3) (2016)
Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
neural network engine with stream architecture and resonant clock mesh. A-SSCC (2016)
Wei Tang, Chia-Hsiang Chen, Zhengya Zhang
2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector. VLSI Circuits (2016)
Chia-Hsiang Chen, Wei Tang, Zhengya Zhang
130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS. ISSCC (2015)
Youn Sung Park, Yaoyu Tao, Zhengya Zhang
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. IEEE J. Solid State Circuits 50 (2) (2015)
Chia-Hsiang Chen, Shiming Song, Zhengya Zhang
An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation. IEEE Trans. Circuits Syst. II Express Briefs (5) (2015)
Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks. VLSIC (2015)
Phil Knag, Jung Kuk Kim, Thomas Chen, Zhengya Zhang
A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding. IEEE J. Solid State Circuits 50 (4) (2015)
Yen-Po Chen, Dongsuk Jeon, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Inhee Lee, Nicholas B. Langhals, Grant H. Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring. IEEE J. Solid State Circuits 50 (1) (2015)
Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors. A-SSCC (2015)
Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang
A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning. VLSIC (2015)
Dongsuk Jeon, Yen-Po Chen, Yoonmyung Lee, Yejoong Kim, Zhiyoong Foo, Grant H. Kruger, Hakan Oral, Omer Berenfeld, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis. ISSCC (2014)
Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang
A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. VLSIC (2014)
Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM. IEEE J. Solid State Circuits 49 (3) (2014)
Farhana Sheikh, Chia-Hsiang Chen, Dongmin Yoon, Borislav Alexandrov, Keith A. Bowman, Anthony Chun, Hossein Alavi, Zhengya Zhang
3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication. SiPS (2014)
Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder. ISSCC (2014)
Dongsuk Jeon, Michael B. Henry, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS. IEEE J. Solid State Circuits 49 (5) (2014)
Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang
A 6.67mW sparse coding ASIC enabling on-chip learning and inference. VLSIC (2014)
Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang
Efficient Hardware Architecture for Sparse Coding. IEEE Trans. Signal Process. 62 (16) (2014)
Chia-Hsiang Chen, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
Design and Evaluation of Confidence-Driven Error-Resilient Systems. IEEE Trans. Very Large Scale Integr. Syst. 22 (8) (2014)
Siddharth Gaba, Phil Knag, Zhengya Zhang, Wei Lu
Memristive devices for stochastic computing. ISCAS (2014)
Chia-Hsiang Chen, Shiming Song, Zhengya Zhang
An FPGA-based transient error simulator for evaluating resilient system designs (abstract only). FPGA (2013)
Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS. ISSCC (2013)
Youn Sung Park, Yaoyu Tao, Zhengya Zhang
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. ISSCC (2013)
Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz
Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED (2013)
Dongsuk Jeon, Yejoong Kim, Inhee Lee, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
A low-power VGA full-frame feature extraction processor. ICASSP (2013)
Chia-Hsiang Chen, Yaoyu Tao, Zhengya Zhang
Efficient in situ error detection enabling diverse path coverage. ISCAS (2013)
Yaoyu Tao, Youn Sung Park, Zhengya Zhang
High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. ISCAS (2012)
Jiadong Wang, Lara Dolecek, Zhengya Zhang, Richard D. Wesel
The Cycle Consistency Matrix Approach to LDPC Absorbing Sets in Separable Circulant-Based Codes CoRR (2012)
Dongsuk Jeon, Mingoo Seok, Zhengya Zhang, David T. Blaauw, Dennis Sylvester
Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Haoran Li, Youn Sung Park, Zhengya Zhang
Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation. FPGA (2012)
Jung Kuk Kim, Jeffrey A. Fessler, Zhengya Zhang
Forward-Projection Architecture for Fast Iterative Image Reconstruction in X-Ray CT. IEEE Trans. Signal Process. 60 (10) (2012)
Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang
38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM. VLSIC (2012)
Matthew Weiner, Borivoje Nikolic, Zhengya Zhang
LDPC decoder architecture for high-data rate personal-area networks. ISCAS (2011)
Jiadong Wang, Lara Dolecek, Zhengya Zhang, Richard D. Wesel
Absorbing set spectrum approach for practical code design. ISIT (2011)
Jiadong Wang, Lara Dolecek, Zhengya Zhang, Richard D. Wesel
Absorbing Set Spectrum Approach for Practical Code Design CoRR (2011)
Chia-Hsiang Chen, Yejoong Kim, Zhengya Zhang, David T. Blaauw, Dennis Sylvester, Helia Naeimi, Sumeet Sandhu
A confidence-driven model for error-resilient computing. DATE (2011)
Jung Kuk Kim, Zhengya Zhang, Jeffrey A. Fessler
Hardware acceleration of iterative image reconstruction for X-ray computed tomography. ICASSP (2011)

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Publication Activity (10 Years)

Top Topics

Top Venues

Zhengya Zhang