Jeongwon Choe

Publication Activity (10 Years)

Years Active: 2020-2024
Publications (10 Years): 8

Top Topics

Content Addressable

Reed Solomon Codes

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

VLSI Technology and Circuits

Publications

Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, Youngjoo Lee
2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications. ISSCC (2024)
Jeongwon Choe, Youngjoo Lee
(7440, 6696) NB-LDPC Decoder over GF(32) using Memory-Reduced Column-Wise Trellis Min-Max Algorithm in 28nm CMOS Technology. VLSI Technology and Circuits (2023)
Jeongwon Choe, Youngjoo Lee
High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm. IEEE J. Solid State Circuits 57 (10) (2022)
Seungwoo Hong, Dongyun Kam, Sangbu Yun, Jeongwon Choe, Namyoon Lee, Youngjoo Lee
Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (4) (2022)
Jeongwon Choe, Youngjoo Lee
A 7Gbps (160, 80) Non-Binary LDPC Decoder with Dual-Message EMS Algorithm in 22nm FinFET Technology. A-SSCC (2021)
Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, Youngjoo Lee
FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks. A-SSCC (2021)
Seungsik Moon, Jeongwon Choe, Youngjoo Lee
Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2020)
Sangbu Yun, Dongyun Kam, Jeongwon Choe, Byeong Yong Kong, Youngjoo Lee
Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm. ISCAS (2020)