Dongyun Kam

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 17

Top Topics

Energy Consumption

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Sangil Han, Jaehee Kim, Dongyun Kam, Byeong Yong Kong, Mijung Kim, Young-Seok Kim, Youngjoo Lee
Constrained Sorter Design using Zero-One Principle. ISCAS (2024)
Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, Youngjoo Lee
2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications. ISSCC (2024)
Ranggi Hwang, Minhoo Kang, Jiwon Lee, Dongyun Kam, Youngjoo Lee, Minsoo Rhu
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks. HPCA (2023)
Jung Gyu Min, Dongyun Kam, Younghoon Byun, Gunho Park, Youngjoo Lee
Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers. ISLPED (2023)
Dongyun Kam, Byeong Yong Kong, Youngjoo Lee
Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (3) (2023)
Minhoo Kang, Ranggi Hwang, Jiwon Lee, Dongyun Kam, Youngjoo Lee, Minsoo Rhu
GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks. CoRR (2022)
Changhyeon Kim, Dongyun Kam, Seokki Kim, Giyoon Park, Youngjoo Lee
Simplified Ordered Statistic Decoding for Short-Length Linear Block Codes. IEEE Commun. Lett. 26 (8) (2022)
Seungwoo Hong, Dongyun Kam, Sangbu Yun, Jeongwon Choe, Namyoon Lee, Youngjoo Lee
Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (4) (2022)
Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. DATE (2022)
Dongyun Kam, Byeong Yong Kong, Youngjoo Lee
Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology. VLSI Technology and Circuits (2022)
Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. CoRR (2021)
Dongyun Kam, Hoyoung Yoo, Youngjoo Lee
Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, Youngjoo Lee
FPGA-Based Ordered Statistic Decoding Architecture for B5G/6G URLLC IIOT Networks. A-SSCC (2021)
Dongyun Kam, Byeong Yong Kong, Youngjoo Lee
Low-Latency Polar Decoder Using Overlapped SCL Processing. ICASSP (2021)
Sangbu Yun, Dongyun Kam, Jeongwon Choe, Byeong Yong Kong, Youngjoo Lee
Ultra-Low-Latency LDPC Decoding Architecture using Reweighted Offset Min-Sum Algorithm. ISCAS (2020)
Seungsik Moon, In-Soo Kim, Dongyun Kam, Dong-Woo Jee, Junil Choi, Youngjoo Lee
Massive MIMO Systems With Low-Resolution ADCs: Baseband Energy Consumption vs. Symbol Detection Performance. IEEE Access 7 (2019)
Dongyun Kam, Youngjoo Lee
Ultra-Low-Latency Parallel SC Polar Decoding Architecture for 5G Wireless Communications. ISCAS (2019)