Sunmean Kim

Publication Activity (10 Years)

Years Active: 2018-2023
Publications (10 Years): 15

Top Topics

Low Power Consumption

Data Conversion

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang
Optimizing Ternary Multiplier Design With Fast Ternary Adder. IEEE Trans. Circuits Syst. II Express Briefs 70 (2) (2023)
Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. DATE (2022)
Minjeong Choi, Youngchang Choi, Sunmean Kim, Seokhyeong Kang
Ternary Sense Amplifier Design for Ternary SRAM. ISOCC (2021)
Youngchang Choi, Sunmean Kim, Kyongsu Lee, Seokhyeong Kang
Design and Analysis of a Low-Power Ternary SRAM. ISCAS (2021)
Dongyun Kam, Jung Gyu Min, Jongho Yoon, Sunmean Kim, Seokhyeong Kang, Youngjoo Lee
Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. CoRR (2021)
Jiyoung Min, Sunmean Kim, Seokhyeong Kang
Memcapacitor based Minimum and Maximum Gate Design. ISOCC (2021)
Sunmean Kim, Yesung Kang, Seunghan Baek, Youngchang Choi, Seokhyeong Kang
Low-Power Ternary Multiplication Using Approximate Computing. IEEE Trans. Circuits Syst. II Express Briefs 68 (8) (2021)
Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, Byoung Hun Lee
Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. ISMVL (2020)
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2020)
Seunghan Baek, Sunmean Kim, Youngchang Choi, Seokhyeong Kang
MTCMOS-based Ternary to Binary Converter. ISOCC (2020)
Youngchang Choi, Sunmean Kim, Seunghan Baek, Seokhyeong Kang
Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion. ISOCC (2020)
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. ISMVL (2019)
Sunghye Park, Sunmean Kim, Seokhyeong Kang
Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU. ISOCC (2019)
Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm. ISMVL (2019)
Sunmean Kim, Taeho Lim, Seokhyeong Kang
An optimal gate design for the synthesis of ternary logic circuits. ASP-DAC (2018)