Kyung Rok Kim

Publication Activity (10 Years)

Years Active: 2003-2023
Publications (10 Years): 5

Top Topics

Cmos Technology

Corner Detectors

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEICE Trans. Electron.

Publications

Young-Eun Choi, Woo-Seok Kim, Myoung Kim, Min-Woo Ryu, Kyung Rok Kim
Low Power and High Density Ternary-SRAM for Always-on Applications. DRC (2023)
Woo-Seok Kim, Young-Eun Choi, Myoung Kim, Min Woo Ryu, Kyung Rok Kim
Energy Efficient Ternary Device in 28-nm CMOS Technology with Excellent Short-Channel Effect Immunity and Variation Tolerance Characteristics. DRC (2023)
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2020)
Sunhae Shin, Esan Jang, Jae Won Jeong, Kyung Rok Kim
CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits. ISMVL (2017)
Yesung Kang, Jaewoo Kim, Sunmin Kim, Sunhae Shin, E-San Jang, Jae Won Jeong, Kyung Rok Kim, Seokhyeong Kang
A Novel Ternary Multiplier Based on Ternary CMOS Compact Model. ISMVL (2017)
Min-Woo Ryu, Sung-Ho Kim, Hee Cheol Hwang, Kibog Park, Kyung Rok Kim
Plasmonic Terahertz Wave Detectors Based on Silicon Field-Effect Transistors. IEICE Trans. Electron. (5) (2013)
Seongjae Cho, In Man Kang, Kyung Rok Kim
Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs. IEICE Electron. Express 7 (19) (2010)
Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic. ISMVL (2003)