Jong Duk Lee

Publication Activity (10 Years)

Years Active: 2003-2009
Publications (10 Years): 0

Publications

Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, Byung-Gook Park
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation. IEICE Trans. Electron. (5) (2009)
Yoon Kim, Seongjae Cho, Gil Sung Lee, Il-Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. IEICE Trans. Electron. (5) (2009)
Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL). IEICE Trans. Electron. (5) (2009)
Jongwook Jeon, Ickhyun Song, Jong Duk Lee, Byung-Gook Park, Hyungcheol Shin
Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design. IEICE Trans. Electron. (5) (2009)
Doo-Hyun Kim, Il-Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. IEICE Trans. Electron. (5) (2009)
Jang-Gn Yun, Il-Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. IEICE Trans. Electron. (5) (2008)
Seongjae Cho, Il-Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). IEICE Trans. Electron. (5) (2008)
Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park
Design and Simulation of Asymmetric MOSFETs. IEICE Trans. Electron. (5) (2007)
Seongjae Cho, Jang-Gn Yun, Il-Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. IEICE Trans. Electron. (5) (2007)
Yong-Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun
Synchronous mirror delay for multiphase locking. IEEE J. Solid State Circuits 39 (1) (2004)
Hyuck In Kwon, In Man Kang, Byung-Gook Park, Jong Duk Lee, Sang Sik Park, Jung Chak Ahn, Yong Hee Lee
Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements. Microelectron. Reliab. 44 (1) (2004)
Woo Young Choi, Jong Duk Lee, Byung-Gook Park
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers. ISLPED (2003)
Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic. ISMVL (2003)