Uk-Rae Cho

Publication Activity (10 Years)

Years Active: 2003-2005
Publications (10 Years): 0

Publications

Kwang-Jin Lee, Hyo-Chang Kim, Uk-Rae Cho, Hyun-Geun Byun, Suki Kim
A Low Jitter ADPLL for Mobile Applications. IEICE Trans. Electron. (6) (2005)
Tae-Hyoung Kim, Kwang-Jin Lee, Uk-Rae Cho, Hyun-Geun Byun
A High Resolution, Wide Range Digital Impedance Controller. IEICE Trans. Electron. (8) (2005)
Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun
Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application. CICC (2005)
Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun
A pseudo-differential CMOS receiver insensitive to input common mode level. ISCAS (1) (2005)
Tae-Hyoung Kim, Uk-Rae Cho, Hyun-Geun Byun
A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch. ISCAS (2) (2005)
Yong-Jin Yoon, Hyuck In Kwon, Jong Duk Lee, Byung Gook Park, Nam-Seog Kim, Uk-Rae Cho, Hyun-Geun Byun
Synchronous mirror delay for multiphase locking. IEEE J. Solid State Circuits 39 (1) (2004)
Kwang-Jin Lee, Cheol Kim, Suki Kim, Uk-Rae Cho, Hyun-Geun Byun
Modeling and Testing of Faults in TCAMs. AsiaSim (2004)
Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun
New dynamic logic-level converters for high performance application. ISCAS (5) (2003)
Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeong-Suk Yang, Kwon-Il Sohn, Sung-Tae Kim, In-Yeol Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, Hyun-Geun Byun
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. IEEE J. Solid State Circuits 38 (11) (2003)
Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun
Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. CICC (2003)