Byung-Gook Park

Publication Activity (10 Years)

Years Active: 2003-2023
Publications (10 Years): 30

Top Topics

Backpropagation Algorithm

Synaptic Weights

Supervised Learning

Top Venues

IEICE Trans. Electron.

Adv. Intell. Syst.

Publications

Min-Hye Oh, Kitae Lee, Sihyun Kim, Byung-Gook Park
Data-driven multi-objective optimization with neural network-based sensitivity analysis for semiconductor devices. Eng. Appl. Artif. Intell. 117 (Part) (2023)
Kannan Udaya Mohanan, Seongjae Cho, Byung-Gook Park
Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application. Appl. Intell. 53 (6) (2023)
Jiseong Im, Jaehyeon Kim, Honam Yoo, Jong-Won Baek, Dongseok Kwon, Seongbin Oh, Jangsaeng Kim, Joon Hwang, Byung-Gook Park, Jong-Ho Lee
On-Chip Trainable Spiking Neural Networks Using Time-To-First-Spike Encoding. IEEE Access 10 (2022)
Honam Yoo, Jong-Won Back, Nam-Hun Kim, Dongseok Kwon, Byung-Gook Park, Jong-Ho Lee
First Demonstration of 1-bit Erase in Vertical NAND Flash Memory. VLSI Technology and Circuits (2022)
Min-Hwi Kim, Sin-Hyung Lee, Sungjun Kim, Byung-Gook Park
A Fast Weight Transfer Method for Real-Time Online Learning in RRAM-Based Neuromorphic System. IEEE Access 10 (2022)
Sungjoon Kim, Jinwoo Park, Tae-Hyeon Kim, Kyungho Hong, Yeongjin Hwang, Byung-Gook Park, Hyungjin Kim
4-bit Multilevel Operation in Overshoot Suppressed Al2O3/TiOx Resistive Random-Access Memory Crossbar Array. Adv. Intell. Syst. 4 (9) (2022)
Seongbin Oh, Soochang Lee, Sung Yun Woo, Dongseok Kwon, Jiseong Im, Joon Hwang, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
Spiking Neural Networks With Time-to-First-Spike Coding Using TFT-Type Synaptic Device Model. IEEE Access 9 (2021)
Dayoung Kim, Tae-Hyeon Kim, Yun-Yeong Choi, Geun-Ho Lee, Jungwon Lee, Wookyung Sun, Byung-Gook Park, Hyungjin Kim, Hyungsoon Shin
Selected Bit-Line Current PUF: Implementation of Hardware Security Primitive Based on a Memristor Crossbar Array. IEEE Access 9 (2021)
Won-Mook Kang, Dongseok Kwon, Sung Yun Woo, Soochang Lee, Honam Yoo, Jangsaeng Kim, Byung-Gook Park, Jong-Ho Lee
Hardware-Based Spiking Neural Network Using a TFT-Type AND Flash Memory Array Architecture Based on Direct Feedback Alignment. IEEE Access 9 (2021)
Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min-Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee
Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks. Adv. Intell. Syst. 3 (8) (2021)
Jangsaeng Kim, Dongseok Kwon, Sung Yun Woo, Won-Mook Kang, Soochang Lee, Seongbin Oh, Chul-Heung Kim, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
Hardware-based spiking neural network architecture using simplified backpropagation algorithm and homeostasis functionality. Neurocomputing 428 (2021)
Hyungyo Kim, Joon Hwang, Dongseok Kwon, Jangsaeng Kim, Min Kyu Park, Jiseong Im, Byung-Gook Park, Jong-Ho Lee
Direct Gradient Calculation: Simple and Variation-Tolerant On-Chip Training Method for Neural Networks. Adv. Intell. Syst. 3 (8) (2021)
Jangsaeng Kim, Dongseok Kwon, Sung Yun Woo, Won-Mook Kang, Soochang Lee, Seongbin Oh, Chul-Heung Kim, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm. Neural Comput. Appl. 33 (15) (2021)
Sung Yun Woo, Dongseok Kwon, Byung-Gook Park, Jong-Ho Lee, Jong-Ho Bae
Pulse-Width Modulation Neuron Implemented by Single Positive-Feedback Device. CoRR (2021)
Min-Woo Kwon, Kyungchul Park, Byung-Gook Park
Low-Power Adaptive Integrate-and-Fire Neuron Circuit Using Positive Feedback FET Co-Integrated With CMOS. IEEE Access 9 (2021)
Seunghwan Song, Bosung Jeon, Sungmin Hwang, Myung-Hyun Baek, Jong-Ho Lee, Byung-Gook Park
Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation. IEEE Access 9 (2021)
Hyeongsu Kim, Jong-Ho Bae, Suhwan Lim, Sungtae Lee, Young-Tak Seo, Dongseok Kwon, Byung-Gook Park, Jong-Ho Lee
Efficient precise weight tuning protocol considering variation of the synaptic devices and target accuracy. Neurocomputing 378 (2020)
Yeon-Joon Choi, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Kyungho Hong, Chae Soo Kim, Sungjun Kim, Seongjae Cho, Byung-Gook Park
/TiN RRAM and Its Effect on Filament Formation Modeled by Monte Carlo Simulation. IEEE Access 8 (2020)
Dong-Hyun Ryu, Tae-Hyung Kim, Taejin Jang, Junsu Yu, Jong-Ho Lee, Byung-Gook Park
Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning. IEEE Access 8 (2020)
Ji-Ho Ryu, Boram Kim, Fayyaz Hussain, Muhammad Ismail, Chandreswar Mahata, Teresa Oh, Muhammad Imran, Kyung Kyu Min, Tae-Hyeon Kim, Byung-Do Yang, Seongjae Cho, Byung-Gook Park, Yoon Kim, Sungjun Kim
Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering. IEEE Access 8 (2020)
Sung Yun Woo, Dongseok Kwon, Nagyong Choi, Won-Mook Kang, Young-Tak Seo, Min Kyu Park, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems. IEEE Access 8 (2020)
Chandreswar Mahata, Wonwoo Kim, Shiwhan Kim, Muhammad Ismail, Min-Hwi Kim, Sungjun Kim, Byung-Gook Park
Reversible nonvolatile and threshold switching characteristics in Cu/high-k/Si devices. IEICE Electron. Express 16 (16) (2019)
Suhwan Lim, Jong-Ho Bae, Jai-Ho Eum, Sungtae Lee, Chul-Heung Kim, Dongseok Kwon, Byung-Gook Park, Jong-Ho Lee
Adaptive learning rule for hardware-based deep neural networks using electronic synapse devices. Neural Comput. Appl. 31 (11) (2019)
Won-Mook Kang, Chul-Heung Kim, Soochang Lee, Sung Yun Woo, Jong-Ho Bae, Byung-Gook Park, Jong-Ho Lee
A Spiking Neural Network with a Global Self-Controller for Unsupervised Learning Based on Spike-Timing-Dependent Plasticity Using Flash Memory Synaptic Devices. IJCNN (2019)
Mihee Uhm, Jin-Moo Lee, Jieun Lee, Jung Han Lee, Sungju Choi, Byung-Gook Park, Dong Myong Kim, Sung-Jin Choi, Hyun-Sun Mo, Yong-Joo Jeong, Dae Hwan Kim
Ultrasensitive Electrical Detection of Hemagglutinin for Point-of-Care Detection of Influenza Virus Based on a CMP-NANA Probe and Top-Down Processed Silicon Nanowire Field-Effect Transistors. Sensors 19 (20) (2019)
Soochang Lee, Chul-Heung Kim, Seongbin Oh, Byung-Gook Park, Jong-Ho Lee
Unsupervised Online Learning With Multiple Postsynaptic Neurons Based on Spike-Timing-Dependent Plasticity Using a TFT-Type NOR Flash Memory Array. CoRR (2018)
Suhwan Lim, Jong-Ho Bae, Jai-Ho Eum, Sungtae Lee, Chul-Heung Kim, Byung-Gook Park, Jong-Ho Lee
Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices. CoRR (2017)
Sungjun Kim, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park
Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell. IEICE Trans. Electron. (5) (2016)
Sungjun Kim, Sunghun Jung, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park
Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals. IEICE Trans. Electron. (5) (2015)
Mina Yun, Seongjae Cho, Sae-Kyoung Kang, Sunghun Jung, Byung-Gook Park
Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect. ISCE (2015)
Seongjae Cho, Sunghun Jung, Sungjun Kim, Byung-Gook Park
Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access. IEICE Electron. Express 11 (4) (2014)
Min-Chul Sun, Sang Wan Kim, Garam Kim, Hyun Woo Kim, Hyungjin Kim, Byung-Gook Park
Novel Tunneling Field-Effect Transistor with Sigma-Shape Embedded SiGe Sources and Recessed Channel. IEICE Trans. Electron. (5) (2013)
Sang Wan Kim, Woo Young Choi, Min-Chul Sun, Hyun Woo Kim, Jongho Lee, Hyungcheol Shin, Byung-Gook Park
L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications. IEICE Trans. Electron. (5) (2013)
Hyungjin Kim, Min-Chul Sun, Hyun Woo Kim, Sang Wan Kim, Garam Kim, Byung-Gook Park
-Control Doping Region. IEICE Trans. Electron. (5) (2012)
Min-Chul Sun, Hyun Woo Kim, Sang Wan Kim, Garam Kim, Hyungjin Kim, Byung-Gook Park
Comparative Study on Top- and Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors. IEICE Trans. Electron. (5) (2012)
Seongjae Cho, Hyungjin Kim, Min-Chul Sun, In Man Kang, Byung-Gook Park, James S. Harris Jr.
Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance. IEICE Electron. Express 9 (9) (2012)
Kyung-Chang Ryoo, Jeong-Hoon Oh, Sunghun Jung, Hyungjin Kim, Byung-Gook Park
Effects of Conductive Defects on Unipolar RRAM for the Improvement of Resistive Switching Characteristics. IEICE Trans. Electron. (5) (2012)
Se Hwan Park, Yoon Kim, Wandong Kim, Joo Yun Seo, Hyungjin Kim, Byung-Gook Park
Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer). IEICE Trans. Electron. (5) (2012)
Myounggon Kang, Ki-Whan Song, Byung-Gook Park, Hyungcheol Shin
The novel SCR-based ESD protection with low triggering and high holding voltages. Microelectron. J. 42 (6) (2011)
Gil Sung Lee, Doo-Hyun Kim, Seongjae Cho, Byung-Gook Park
A New 1T DRAM Cell: Cone Type 1T DRAM Cell. IEICE Trans. Electron. (5) (2011)
Seongjae Cho, Jung Hoon Lee, Yoon Kim, Jang-Gn Yun, Hyungcheol Shin, Byung-Gook Park
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices. IEICE Trans. Electron. (5) (2010)
Dong-Seup Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jung Han Lee, Seongjae Cho, Byung-Gook Park
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer. IEICE Trans. Electron. (5) (2010)
Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, Byung-Gook Park
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation. IEICE Trans. Electron. (5) (2009)
Yoon Kim, Seongjae Cho, Gil Sung Lee, Il-Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. IEICE Trans. Electron. (5) (2009)
Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho
Nanosculpture: Three-dimensional CMOS device structures for the ULSI era. Microelectron. J. 40 (4-5) (2009)
Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL). IEICE Trans. Electron. (5) (2009)
Jongwook Jeon, Ickhyun Song, Jong Duk Lee, Byung-Gook Park, Hyungcheol Shin
Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design. IEICE Trans. Electron. (5) (2009)
Doo-Hyun Kim, Il-Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. IEICE Trans. Electron. (5) (2009)
Jang-Gn Yun, Il-Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. IEICE Trans. Electron. (5) (2008)
Seongjae Cho, Il-Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). IEICE Trans. Electron. (5) (2008)
Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park
Design and Simulation of Asymmetric MOSFETs. IEICE Trans. Electron. (5) (2007)
Seongjae Cho, Jang-Gn Yun, Il-Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. IEICE Trans. Electron. (5) (2007)
Hyuck In Kwon, In Man Kang, Byung-Gook Park, Jong Duk Lee, Sang Sik Park, Jung Chak Ahn, Yong Hee Lee
Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements. Microelectron. Reliab. 44 (1) (2004)
Woo Young Choi, Jong Duk Lee, Byung-Gook Park
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers. ISLPED (2003)
Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic. ISMVL (2003)