Myounggon Kang

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 5

Top Topics

Silicon Nitride

Genetic Algorithm

Top Venues

IEICE Electron. Express

Publications

Jun Hui Park, Jung Nam Kim, Seonhaeng Lee, Gang-Jun Kim, Namhyun Lee, Rock-Hyun Baek, Dae Hwan Kim, Changhyun Kim, Myounggon Kang, Yoon Kim
Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning. IEEE Access 12 (2024)
Sueyeon Kim, Insoo Choi, Sangki Cho, Myounggon Kang, Seungjae Baik, Changho Ra, Jongwook Jeon
Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET). IEEE Access 11 (2023)
Duckhoon Ro, Changhong Min, Myounggon Kang, Ik Joon Chang, Hyung-Min Lee
A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems. Sensors 20 (1) (2020)
Younghwan Son, Yoon Kim, Myounggon Kang
Investigation of capture and emission dependence between individual traps from complex random telegraph signal noise analysis. IEICE Electron. Express 14 (2) (2017)
Younghwan Son, Yoon Kim, Myounggon Kang
Characterization of oxide trap density with the charge pumping technique in dual-layer gate oxide. IEICE Electron. Express 14 (8) (2017)
Myounggon Kang, Ki-Whan Song, Byung-Gook Park, Hyungcheol Shin
The novel SCR-based ESD protection with low triggering and high holding voltages. Microelectron. J. 42 (6) (2011)
Myounggon Kang, Ki-Tae Park, Youngsun Song, Sungsoo Lee, Yunheub Song, Youngho Lim
A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory. IEICE Trans. Electron. (2) (2010)
Ki-Tae Park, Youngsun Song, Myounggon Kang, Sungsoo Lee, Youngho Lim, Kang-Deog Suh, Chilhee Chung
Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories. IEEE J. Solid State Circuits 45 (10) (2010)
Youngsun Song, Ki-Tae Park, Myounggon Kang, Yunheub Song, Sungsoo Lee, Youngho Lim, Kang-Deog Suh
Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory. IEICE Trans. Electron. (3) (2010)
Ki-Tae Park, Myounggon Kang, Soonwook Hwang, Doo-Gon Kim, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-hoon Jang, Hansoo Kim, Yeong-Taek Lee, Soon-Moon Jung, Changhyun Kim
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure. IEEE J. Solid State Circuits 44 (1) (2009)
Ki-Tae Park, Myounggon Kang, Doogon Kim, Soonwook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, Kinam Kim
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories. IEEE J. Solid State Circuits 43 (4) (2008)
Ki-Tae Park, Doo-Gon Kim, Soonwook Hwang, Myounggon Kang, Hoosung Cho, Youngwook Jeong, Yong-Il Seo, Jae-hoon Jang, Hansoo Kim, Soon-Moon Jung, Yeong-Taek Lee, Changhyun Kim, Won-Seong Lee
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure. ISSCC (2008)