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A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories.

Ki-Tae ParkMyounggon KangDoogon KimSoonwook HwangByung Yong ChoiYeong-Taek LeeChanghyun KimKinam Kim
Published in: IEEE J. Solid State Circuits (2008)
Keyphrases
  • inter cell
  • digital images
  • associative memory
  • master slave
  • multi core processors
  • real time
  • website
  • data structure
  • management system
  • database management systems
  • parallel implementation
  • parallel architecture