Byung-Do Yang

Publication Activity (10 Years)

Years Active: 2001-2023
Publications (10 Years): 13

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Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Hyeong-Ju Kang, Byung-Do Yang
AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning. Sensors 23 (19) (2023)
Ki-Chan Woo, Byung-Do Yang
0.3-V RC-to-Digital Converter Using a Negative Charge-Pump Switch. IEEE Trans. Circuits Syst. II Express Briefs (2) (2020)
Ki-Chan Woo, Byung-Do Yang
A 0.35V 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit. IEEE Trans. Circuits Syst. (12) (2020)
Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang
Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Ki-Chan Woo, Byung-Do Yang
A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain. IEEE Trans. Circuits Syst. II Express Briefs (7) (2020)
Ji-Ho Ryu, Boram Kim, Fayyaz Hussain, Muhammad Ismail, Chandreswar Mahata, Teresa Oh, Muhammad Imran, Kyung Kyu Min, Tae-Hyeon Kim, Byung-Do Yang, Seongjae Cho, Byung-Gook Park, Yoon Kim, Sungjun Kim
Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering. IEEE Access 8 (2020)
Dae-Jin Kim, Tae-Hyeong Kim, Hyeon-Sam Shin, Bo-Seok Seo, Mi-Jeong Kim, Byung-Do Yang
A Voltage-Mode Buck Converter With a Reduced Type-I Compensation Capacitor Using an Error-Amplifier Current-Sampling Scheme. ICEIC (2019)
Soo-Yeon Shin, Dong-Myung Kim, Byung-Do Yang, Chansik Park, Jae-Won Suh
Depth Map Estimation Model with Efficient Feature Extraction Module. ICEIC (2019)
Tae-Hyeong Kim, Dae-Jin Kim, Hyeon-Sam Shin, Sang-Ho Lee, Jae-Won Suh, Byung-Do Yang
Low Power Digital PWM Buck Converter With a Clock-Gating Shift-Register. ICEIC (2019)
Ki-Chan Woo, Jae-Mun Oh, Byung-Do Yang
DC-DC Buck Converter Using Analog Coarse-Fine Self-Tracking Zero-Current Detection Scheme. IEEE Trans. Circuits Syst. II Express Briefs (11) (2019)
Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches. IEEE Trans. Circuits Syst. II Express Briefs (8) (2019)
Ki-Chan Woo, Byung-Do Yang
Low-Area TCAM Using A Don't Care Reduction Scheme. IEEE J. Solid State Circuits 53 (8) (2018)
Jaekwon Lee, Kisub Kim, Yonghyeon Lee, Jang-Eui Hong, Young-Hoon Seo, Byung-Do Yang, Woosung Jung
Extracting the Source Code Context to Predict Import Changes using GPES. KSII Trans. Internet Inf. Syst. 11 (2) (2017)
Byung-Do Yang
Low-Power and Area-Efficient Shift Register Using Pulsed Latches. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2015)
Byung-Do Yang
Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme. IEEE J. Solid State Circuits 50 (10) (2015)
Byung-Do Yang
250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit. IEEE Trans. Circuits Syst. II Express Briefs (11) (2014)
Hyeong-Ju Kang, Byung-Do Yang
Low-Power Time Deinterleaver for ISDB-T Receiver. IEEE Trans. Circuits Syst. II Express Briefs (10) (2012)
Hyeong-Ju Kang, Seung Jae Lee, Byung-Do Yang
Area-Efficient Prefilter Architecture for a CDMA Receiver. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Byung-Do Yang, Yong-Kyu Lee, Si-Woo Sung, Jae-Joong Min, Jae-Mun Oh, Hyeong-Ju Kang
A Low Power Content Addressable Memory Using Low Swing Search Lines. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2011)
Byung-Do Yang
A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Byung-Do Yang
A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations. IEEE J. Solid State Circuits 45 (10) (2010)
Jang-Su Kim, Yong-Kyu Lee, Jee-Sue Lee, Young-Kyu Shin, Jung-Hyun Tark, Keun-Chul Ryu, Byung-Do Yang
A Fast-switching Current-pulse Driver for LED Backlight. ISCAS (2009)
Byung-Do Yang, Jang-Su Kim, Jin-Kuk Yun, Yong-Kyu Lee, Jee-Sue Lee
A highly accurate BiCMOS cascode current mirror for wide output voltage range. ISCAS (2008)
Byung-Do Yang, Jae-Eun Lee, Jang-Su Kim, Junghyun Cho, Seung-Yun Lee, Byoung-Gon Yu
A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme. ISCAS (2007)
Byung-Do Yang, Lee-Sup Kim
A low-power ROM using single charge-sharing capacitor and hierarchical bit line. IEEE Trans. Very Large Scale Integr. Syst. 14 (4) (2006)
Byung-Do Yang, Lee-Sup Kim
A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver. IEEE J. Solid State Circuits 40 (8) (2005)
Byung-Do Yang, Lee-Sup Kim
A low-power SRAM using hierarchical bit line and local sense amplifiers. IEEE J. Solid State Circuits 40 (6) (2005)
Byung-Do Yang, Jang-Hong Choi, Seon-Ho Han, Lee-Sup Kim, Hyun-Kyu Yu
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. IEEE J. Solid State Circuits 39 (5) (2004)
Byung-Do Yang, Lee-Sup Kim
An error pattern ROM compression method for continuous data. ISCAS (2) (2004)
Byung-Do Yang, Lee-Sup Kim
A low-power ROM using charge recycling and charge sharing techniques. IEEE J. Solid State Circuits 38 (4) (2003)
Byung-Do Yang, Lee-Sup Kim
A low power charge sharing ROM using dummy bit lines. ISCAS (5) (2003)
Byung-Do Yang, Lee-Sup Kim
A low-power charge-recycling ROM architecture. IEEE Trans. Very Large Scale Integr. Syst. 11 (4) (2003)
Byung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu
A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. ISCAS (5) (2002)
Byung-Do Yang, Lee-Sup Kim
A ROM compression method for continuous data. CICC (2002)
Byung-Do Yang, Lee-Sup Kim
A low power charge-recycling ROM architecture. ISCAS (4) (2001)