A low-power charge-recycling ROM architecture.
Byung-Do YangLee-Sup KimPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2003)
Keyphrases
- low power
- vlsi architecture
- power consumption
- low cost
- high speed
- cmos technology
- mixed signal
- single chip
- nm technology
- high power
- digital signal processing
- logic circuits
- real time
- gate array
- signal processor
- wireless transmission
- low power consumption
- vlsi implementation
- cmos image sensor
- vlsi circuits
- power dissipation
- data flow
- general purpose
- power reduction