A low-power SRAM using hierarchical bit line and local sense amplifiers.

Byung-Do Yang Lee-Sup Kim

Published in: IEEE J. Solid State Circuits (2005)

Keyphrases

low power
high power
power consumption
low cost
high speed
single chip
wireless transmission
vlsi architecture
power reduction
low power consumption
cmos technology
nm technology
logic circuits
digital signal processing
power management
mixed signal
image sensor
main memory
gate array