A low-power ROM using single charge-sharing capacitor and hierarchical bit line.

Byung-Do Yang Lee-Sup Kim

Published in: IEEE Trans. Very Large Scale Integr. Syst. (2006)

Keyphrases

low power
power consumption
low cost
high speed
single chip
high power
logic circuits
vlsi architecture
low power consumption
vlsi circuits
wireless transmission
digital signal processing
image sensor
gate array
general purpose
signal processor
analog to digital converter
wireless sensor networks