Hyeong-Ju Kang

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 9

Top Topics

Pruning Algorithm

Parallel Implementation

Convolutional Neural Networks

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. Video Technol.

Publications

Hyeong-Ju Kang, Byung-Do Yang
AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning. Sensors 23 (19) (2023)
Hyeong-Ju Kang
AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture. FPGA (2023)
Hyeong-Ju Kang
AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture. CoRR (2022)
Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang
Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Hyeong-Ju Kang
Accelerator-Aware Pruning for Convolutional Neural Networks. IEEE Trans. Circuits Syst. Video Technol. 30 (7) (2020)
Hyeong-Ju Kang
Real-Time Object Detection on 640x480 Image With VGG16+SSD. FPT (2019)
Hyeong-Ju Kang
Short floating-point representation for convolutional neural network inference. IEICE Electron. Express 16 (2) (2019)
Ki-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang
Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches. IEEE Trans. Circuits Syst. II Express Briefs (8) (2019)
Hyeong-Ju Kang
Accelerator-Aware Pruning for Convolutional Neural Networks. CoRR (2018)
Hyeong-Ju Kang, Hee Suk Seo, Jin Kwak
Area-efficient convolutional deinterleaver for mobile TV receiver. ACM Trans. Embed. Comput. Syst. 12 (2) (2013)
Hyeong-Ju Kang, Byung-Do Yang
Low-Power Time Deinterleaver for ISDB-T Receiver. IEEE Trans. Circuits Syst. II Express Briefs (10) (2012)
Hyeong-Ju Kang, Seung Jae Lee, Byung-Do Yang
Area-Efficient Prefilter Architecture for a CDMA Receiver. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Byung-Do Yang, Yong-Kyu Lee, Si-Woo Sung, Jae-Joong Min, Jae-Mun Oh, Hyeong-Ju Kang
A Low Power Content Addressable Memory Using Low Swing Search Lines. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2011)
Hyeong-Ju Kang, In-Cheol Park
SAT-based unbounded symbolic model checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (2) (2005)
Hyeong-Ju Kang, Yongwoo Choi, Kimo Kim, In-Cheol Park, Jung-Wook Kim, Eul-Hwan Lee, Goo-Soo Gahang
A scalable SIMD digital signal processor for high-quality multifunctional printer systems. Color Imaging: Processing, Hardcopy, and Applications (2005)
Sung-Won Lee, Hyeong-Ju Kang, In-Cheol Park
A 24-bit floating-point audio DSP controller supporting fast exponentiation. ISCAS (2) (2003)
Hyeong-Ju Kang, In-Cheol Park
SAT-based unbounded symbolic model checking. DAC (2003)
Hyeong-Ju Kang, In-Cheol Park
Pairing and ordering to reduce hardware complexity in cascade form filter design. ISCAS (4) (2003)
Hyeong-Ju Kang, In-Cheol Park
A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure. ICASSP (2002)
In-Cheol Park, Hyeong-Ju Kang
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (12) (2002)
Hyeong-Ju Kang, In-Cheol Park
Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. ISCAS (2) (2001)
In-Cheol Park, Hyeong-Ju Kang
Digital Filter Synthesis Based on Minimal Signed Digit Representation. DAC (2001)
Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. ICCAD (2000)