In-Cheol Park

ORCID

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 46

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Commun. Lett.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Boseon Jang, Hyejung Jang, Sungho Kim, Kangjoon Choi, In-Cheol Park
Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (6) (2024)
Suchang Kim, Boseon Jang, Jaeyoung Lee, Hyungjoon Bae, Hyejung Jang, In-Cheol Park
A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (4) (2023)
Hyungjoon Bae, Yujin Hyun, Suchang Kim, Sangsoo Park, Jaeyoung Lee, Boseon Jang, Suyoung Choi, In-Cheol Park
High-Speed Counter With Novel LFSR State Extension. IEEE Trans. Computers 72 (3) (2023)
Jaehyeon Park, Jaeyoung Lee, In-Cheol Park
In Situ Multi-Bit Decision for Successive Cancellation List Decoding of Polar Codes. IEEE Access 10 (2022)
Seongjin Lee, Sangsoo Park, Boseon Jang, In-Cheol Park
Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (5) (2022)
Suchang Kim, Seungho Na, Byeong Yong Kong, Jaewoong Choi, In-Cheol Park
Real-Time SSDLite Object Detection on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Yujin Hyun, In-Cheol Park
Constant-Time Synchronous Binary Counter With Minimal Clock Period. IEEE Trans. Circuits Syst. II Express Briefs 68 (7) (2021)
Suchang Kim, Jihyuck Jo, In-Cheol Park
Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (5) (2021)
Wooyoung Kim, Yujin Hyun, Jaeyoung Lee, In-Cheol Park
Interleaved Local Sorting for Successive Cancellation List Decoding of Polar Codes. IEEE Access 9 (2021)
Byeong Yong Kong, In-Cheol Park
A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access. IEEE Trans. Circuits Syst. II Express Briefs (3) (2020)
Jaewoong Choi, Byeong Yong Kong, In-Cheol Park
Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2020)
Byeong Yong Kong, Jooseung Lee, In-Cheol Park
A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis. ISCAS (2020)
Byeong Yong Kong, Jooseung Lee, In-Cheol Park
A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Kyungpil Lee, In-Cheol Park
Large-Small Sorting for Successive Cancellation List Decoding of Polar Codes. IEEE Access 8 (2020)
Byeong Yong Kong, In-Cheol Park
A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access. ISCAS (2020)
Seokha Hwang, Seungsik Moon, Jaehwan Jung, Daesung Kim, In-Cheol Park, Jeongseok Ha, Youngjoo Lee
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2019)
Byeong Yong Kong, In-Cheol Park
Parallel IDMA Architecture Based on Interleaving with Replicated Subpatterns. ICC (2019)
Byeong Yong Kong, Jaehwan Jung, In-Cheol Park
Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors. ICECS (2018)
Daesung Kim, In-Cheol Park
A Fast Successive Cancellation List Decoder for Polar Codes With an Early Stopping Criterion. IEEE Trans. Signal Process. 66 (18) (2018)
Jaehwan Jung, In-Cheol Park, Youngjoo Lee
A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems. ASP-DAC (2018)
Byeong Yong Kong, In-Cheol Park
Efficient Implementation of Multiple Interleavers in IDMA for 5G. ISOCC (2018)
Jihyuck Jo, Soyoung Cha, Dayoung Rho, In-Cheol Park
DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks. IEEE J. Solid State Circuits 53 (2) (2018)
Byeong Yong Kong, In-Cheol Park
A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading. IEEE J. Solid State Circuits 53 (11) (2018)
Daesung Kim, Injae Yoo, In-Cheol Park
Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture. IEEE Trans. Circuits Syst. II Express Briefs (6) (2018)
Jihyuck Jo, Suchang Kim, In-Cheol Park
Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Injae Yoo, In-Cheol Park
Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks. IEEE Trans. Circuits Syst. II Express Briefs (9) (2017)
Byeong Yong Kong, In-Cheol Park
Improved Sorting Architecture for K-Best MIMO Detection. IEEE Trans. Circuits Syst. II Express Briefs (9) (2017)
Saedong Yeo, In-Cheol Park
Improved Hard-Reliability Based Majority-Logic Decoding for Non-Binary LDPC Codes. IEEE Commun. Lett. 21 (1) (2017)
Jooseung Lee, In-Cheol Park
High-Performance Low-Area Video Up-Scaling Architecture for 4-K UHD Video. IEEE Trans. Circuits Syst. II Express Briefs (4) (2017)
Jaejoon Choi, In-Cheol Park
Improved Successive-Cancellation Decoding of Polar Codes Based on Recursive Syndrome Decomposition. IEEE Commun. Lett. 21 (11) (2017)
Jaehwan Jung, In-Cheol Park
Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems. IEEE Commun. Lett. 21 (5) (2017)
Jihyuck Jo, In-Cheol Park
Low-Latency Low-Cost Architecture for Square and Cube Roots. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2017)
Seokha Hwang, Jaehwan Jung, Daesung Kim, Jeongseok Ha, In-Cheol Park, Youngjoo Lee
An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages. A-SSCC (2017)
Hoyoung Yoo, In-Cheol Park
Efficient Pruning for Successive-Cancellation Decoding of Polar Codes. IEEE Commun. Lett. 20 (12) (2016)
Byeong Yong Kong, Hoyoung Yoo, In-Cheol Park
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs (7) (2016)
Jaejoon Choi, Jaehwan Jung, In-Cheol Park
Area-Efficient Approach for Generating Quantized Gaussian Noise. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2016)
Youngjoo Lee, Jaehwan Jung, In-Cheol Park
Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems. IEICE Trans. Electron. (2) (2016)
Byeong Yong Kong, In-Cheol Park
Low-complexity symbol detection for massive MIMO uplink based on Jacobi method. PIMRC (2016)
Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach. IEEE Trans. Circuits Syst. II Express Briefs (3) (2016)
Jihyuck Jo, Hoyoung Yoo, In-Cheol Park
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. IEEE Trans. Very Large Scale Integr. Syst. 24 (2) (2016)
Injae Yoo, Mina Hwang, Jaehwan Jung, Suhyun Kim, In-Cheol Park
Unidirectional ring ethernet for low-complexity in-vehicle control network. ICIT (2015)
Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
Efficient Parallel Architecture for Linear Feedback Shift Registers. IEEE Trans. Circuits Syst. II Express Briefs (11) (2015)
Youngjoo Lee, Bongjin Kim, Jaehwan Jung, In-Cheol Park
Low-Complexity Tree Architecture for Finding the First Two Minima. IEEE Trans. Circuits Syst. II Express Briefs (1) (2015)
Hoyoung Yoo, In-Cheol Park
Partially Parallel Encoder Architecture for Long Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs (3) (2015)
Byeong Yong Kong, In-Cheol Park
Narrow-range frequency estimation based on comprehensive optimization of DFT and interpolation. ICASSP (2015)
Injae Yoo, Bongjin Kim, In-Cheol Park
Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2015)
Byeong Yong Kong, Jihyuck Jo, Hyewon Jeong, Mina Hwang, Soyoung Cha, Bongjin Kim, In-Cheol Park
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. 22 (7) (2014)
Injae Yoo, In-Cheol Park
A search-less DEC BCH decoder for low-complexity fault-tolerant systems. SiPS (2014)
Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives. IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
7.3 Gb/s universal BCH encoder and decoder for SSD controllers. ASP-DAC (2014)
Injae Yoo, Bongjin Kim, In-Cheol Park
Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Injae Yoo, Bongjin Kim, In-Cheol Park
Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes. VTC Spring (2013)
Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. IEEE J. Solid State Circuits 48 (10) (2013)
Byeong Yong Kong, In-Cheol Park
Efficient Tree-Traversal Strategy for Soft-Output MIMO Detection Based on Candidate-Set Reorganization. IEEE Commun. Lett. 17 (9) (2013)
Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park
Area-Efficient Multimode Encoding Architecture for Long BCH Codes. IEEE Trans. Circuits Syst. II Express Briefs (12) (2013)
Youngjoo Lee, Hoyoung Yoo, In-Cheol Park
100b error-correcting BCH decoder in 0.13µm CMOS process. ASP-DAC (2013)
Bongjin Kim, Injae Yoo, In-Cheol Park
Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns. IEEE Trans. Circuits Syst. II Express Briefs (3) (2013)
Byeong Yong Kong, In-Cheol Park
Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors. VTC Spring (2013)
Bongjin Kim, In-Cheol Park
Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division. IEICE Trans. Commun. (7) (2013)
Youngjoo Lee, Hoyoung Yoo, In-Cheol Park
Small-area parallel syndrome calculation for strong BCH decoding. ICASSP (2012)
Injae Yoo, In-Cheol Park
SNR-Adaptive Input Quantization for Turbo Decoding. VTC Spring (2012)
Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
Low-latency area-efficient decoding architecture for shortened reed-solomon codes. ISOCC (2012)
Kangwoo Park, In-Cheol Park
Low-Complexity Tone Reservation for PAPR Reduction in OFDM Communication Systems. IEEE Trans. Very Large Scale Integr. Syst. 20 (10) (2012)
Byeong Yong Kong, In-Cheol Park
FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (8) (2012)
Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park
6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers. ISSCC (2012)
Injae Yoo, Bongjin Kim, In-Cheol Park
Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding. IEEE Commun. Lett. 16 (12) (2012)
Youngjoo Lee, Jinook Song, In-Cheol Park
Statistical modeling of capacitor mismatch effects for successive approximation register ADCs. ISOCC (2011)
Tae-Hwan Kim, In-Cheol Park
Efficient Pruning for Infinity-Norm Sphere Decoding Based on Schnorr-Euchner Enumeration. IEICE Trans. Commun. (9) (2011)
Youngjoo Lee, Hoyoung Yoo, In-Cheol Park
Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization. IEEE Trans. Circuits Syst. II Express Briefs (8) (2011)
Jinook Song, In-Cheol Park
Division-less high-radix interleaved modular multiplication using a scaled modulus. ISOCC (2011)
Bongjin Kim, In-Cheol Park
QC-LDPC Decoding Architecture based on Stride Scheduling. ISCAS (2011)
Kangwoo Park, In-Cheol Park
Low-complexity tone reservation method for PAPR reduction of OFDM systems. ISCAS (2010)
Bongjin Kim, Hasan Ahmed, In-Cheol Park
Dual-rail decoding of low-density parity-check codes. ISCAS (2010)
Tae-Hwan Kim, In-Cheol Park
near-optimal MIMO detector in 0.18µm CMOS. CICC (2010)
In-Cheol Park, Tae-Hwan Kim
Multiplier-less and Table-less Linear Approximation for Square-Related Functions. IEICE Trans. Inf. Syst. (11) (2010)
Youngjoo Lee, In-Cheol Park
Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters. ISCAS (2010)
Tae-Hwan Kim, Youngjoo Lee, In-Cheol Park
Design of a Scalable and Programmable Sound Synthesizer. IEEE Trans. Very Large Scale Integr. Syst. 18 (6) (2010)
Tae-Hwan Kim, In-Cheol Park
Small-Area and Low-Energy K -Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2010)
Minsoo Rhu, In-Cheol Park
Optimization of Arithmetic Coding for JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 20 (3) (2010)
Youngjoo Lee, Goeun Lim, In-Cheol Park
Low-complex BPSK demodulation using absolute comparison. ICECS (2010)
Tae-Hwan Kim, In-Cheol Park
-best MIMO detector using relaxed tree expansion and early forwarding. ISLPED (2010)
Jinook Song, In-Cheol Park
Spur-Free MASH Delta-Sigma Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2010)
Tae-Hwan Kim, In-Cheol Park
High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstra's Search. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2010)
Tae-Hwan Kim, Youngjoo Lee, In-Cheol Park
A Scalable and Programmable Sound Synthesizer. ISCAS (2009)
Jinook Song, In-Cheol Park
Novel Pipelined DWT Architecture for Dual-line Scan. ISCAS (2009)
In-Cheol Park, Tae-Hwan Kim
Multiplier-less and table-less linear approximation for square and square-root. ICCD (2009)
Ji-Hoon Kim, In-Cheol Park
A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE. CICC (2009)
Kangwoo Park, In-Cheol Park
Fast Frequency Acquisition Phase Frequency Detectors with Prediction-based edge Blocking. ISCAS (2009)
Tae-Hwan Kim, In-Cheol Park
Implementation of a High-Throughput and Area-Efficient MIMO Detector Based on Modified Dijkstra's Search. GLOBECOM (2009)
Ji-Hoon Kim, In-Cheol Park
Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes. IEEE Trans. Circuits Syst. II Express Briefs (1) (2009)
Minsoo Rhu, In-Cheol Park
Memory-less bit-plane coder architecture for JPEG2000 with concurrent column-stripe coding. ICIP (2009)
Jinook Song, In-Cheol Park
Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines. IEEE Trans. Circuits Syst. II Express Briefs (12) (2009)
Minsoo Rhu, In-Cheol Park
Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000. ICIP (2009)
Minsoo Rhu, In-Cheol Park
A novel trace-pipelined binary arithmetic coder architecture for JPEG2000. SiPS (2009)
Tae-Hwan Kim, In-Cheol Park
Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems. ASP-DAC (2008)
Jeong-Sup Lee, In-Cheol Park
Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. ISCAS (2008)
Jeong-Ho Han, In-Cheol Park
FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (5) (2008)
Ji-Hoon Kim, In-Cheol Park
Duo-binary circular turbo decoder based on border metric encoding for WiMAX. ASP-DAC (2008)
Hae-Soo Jeon, Duk-Hyun You, In-Cheol Park
Fast frequency acquisition all-digital PLL using PVT calibration. ISCAS (2008)
Jeong-Ho Han, In-Cheol Park
Digital filter synthesis considering multiple adder graphs for a coefficient. ICCD (2008)

In-Cheol Park.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

In-Cheol Park