Jaehwan Jung

Publication Activity (10 Years)

Years Active: 2013-2019
Publications (10 Years): 7

Top Topics

Error Concealment

Storage Systems

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Seokha Hwang, Seungsik Moon, Jaehwan Jung, Daesung Kim, In-Cheol Park, Jeongseok Ha, Youngjoo Lee
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2019)
Byeong Yong Kong, Jaehwan Jung, In-Cheol Park
Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors. ICECS (2018)
Jaehwan Jung, In-Cheol Park, Youngjoo Lee
A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems. ASP-DAC (2018)
Jaehwan Jung, In-Cheol Park
Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems. IEEE Commun. Lett. 21 (5) (2017)
Seokha Hwang, Jaehwan Jung, Daesung Kim, Jeongseok Ha, In-Cheol Park, Youngjoo Lee
An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages. A-SSCC (2017)
Jaejoon Choi, Jaehwan Jung, In-Cheol Park
Area-Efficient Approach for Generating Quantized Gaussian Noise. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2016)
Youngjoo Lee, Jaehwan Jung, In-Cheol Park
Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems. IEICE Trans. Electron. (2) (2016)
Injae Yoo, Mina Hwang, Jaehwan Jung, Suhyun Kim, In-Cheol Park
Unidirectional ring ethernet for low-complexity in-vehicle control network. ICIT (2015)
Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, In-Cheol Park
Efficient Parallel Architecture for Linear Feedback Shift Registers. IEEE Trans. Circuits Syst. II Express Briefs (11) (2015)
Youngjoo Lee, Bongjin Kim, Jaehwan Jung, In-Cheol Park
Low-Complexity Tree Architecture for Finding the First Two Minima. IEEE Trans. Circuits Syst. II Express Briefs (1) (2015)
Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. IEEE J. Solid State Circuits 48 (10) (2013)
Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park
Area-Efficient Multimode Encoding Architecture for Long BCH Codes. IEEE Trans. Circuits Syst. II Express Briefs (12) (2013)