A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory.
Youngjoo LeeHoyoung YooJaehwan JungJihyuck JoIn-Cheol ParkPublished in: IEEE J. Solid State Circuits (2013)
Keyphrases
- flash memory
- random access memory
- solid state
- reed solomon
- garbage collection
- embedded systems
- main memory
- file system
- random access
- buffer management
- disk drives
- b tree
- data storage
- high speed
- successive approximation
- nm technology
- storage devices
- hand held devices
- database systems
- storage systems
- power consumption
- low cost
- memory management
- data structure
- cmos technology
- small size
- error concealment
- metal oxide semiconductor
- low voltage
- database
- analog to digital converter