Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks.
Injae YooIn-Cheol ParkPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2017)
Keyphrases
- low density parity check
- low power
- vlsi architecture
- ldpc codes
- decoding algorithm
- power consumption
- high speed
- low cost
- nm technology
- error correction
- channel coding
- cmos technology
- mixed signal
- single chip
- low complexity
- vlsi circuits
- real time
- power dissipation
- associative memory
- vlsi implementation
- physical layer
- message passing
- low power consumption
- distributed video coding
- channel capacity
- turbo codes
- logic circuits
- image sensor
- computer simulation
- ultra low power