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Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division.

Bongjin KimIn-Cheol Park
Published in: IEICE Trans. Commun. (2013)
Keyphrases
  • real time
  • limited memory
  • memory requirements
  • scheduling algorithm
  • associative memory
  • decoding algorithm
  • turbo codes
  • ldpc codes