A low power charge-recycling ROM architecture.
Byung-Do YangLee-Sup KimPublished in: ISCAS (4) (2001)
Keyphrases
- low power
- vlsi architecture
- power consumption
- low cost
- high speed
- single chip
- cmos technology
- mixed signal
- high power
- wireless transmission
- logic circuits
- nm technology
- digital signal processing
- low power consumption
- design considerations
- real time
- gate array
- power reduction
- vlsi circuits
- image sensor
- delay insensitive
- signal processor
- ultra low power
- computer simulation
- image processing