Seongjae Cho

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 8

Top Topics

Field Effect Transistors

Monte Carlo Simulation

Top Venues

IEICE Trans. Electron.

Publications

Soomin Kim, Seongjae Cho
Effects of Misaligned Gate Lapping Over the Channel on Performances of Ultra-Thin Vertical-Pillar MOSFET. ICEIC (2024)
Kannan Udaya Mohanan, Seongjae Cho, Byung-Gook Park
Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application. Appl. Intell. 53 (6) (2023)
Arati Kumari Shah, Eou-Sik Cho, Jisun Park, Hyungsoon Shin, Seongjae Cho
A Compact Integrate-and-Fire Neuron Circuit Embedding Operational Transconductance Amplifier for Fidelity Enhancement. IEEE Access 11 (2023)
Dongyeon Kang, Jun Tae Jang, Shinyoung Park, Md. Hasan Raza Ansari, Jong-Ho Bae, Sung-Jin Choi, Dong Myong Kim, Changwook Kim, Seongjae Cho, Dae Hwan Kim
Threshold-Variation-Tolerant Coupling-Gate α-IGZO Synaptic Transistor for More Reliably Controllable Hardware Neuromorphic System. IEEE Access 9 (2021)
Yeon-Joon Choi, Min-Hwi Kim, Suhyun Bang, Tae-Hyeon Kim, Dong Keun Lee, Kyungho Hong, Chae Soo Kim, Sungjun Kim, Seongjae Cho, Byung-Gook Park
/TiN RRAM and Its Effect on Filament Formation Modeled by Monte Carlo Simulation. IEEE Access 8 (2020)
Ji-Ho Ryu, Boram Kim, Fayyaz Hussain, Muhammad Ismail, Chandreswar Mahata, Teresa Oh, Muhammad Imran, Kyung Kyu Min, Tae-Hyeon Kim, Byung-Do Yang, Seongjae Cho, Byung-Gook Park, Yoon Kim, Sungjun Kim
Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering. IEEE Access 8 (2020)
Jae Yoon Lee, Youngmin Kim, Ikhyeon Kworn, Il Hwan Cho, Jae Yeon Lee, Soo Gil Kim, Seongjae Cho
Fabrication and Characterization of a Fully Si Compatible Forming-Free GeOxResistive Switching Random-Access Memory. DRC (2018)
Sungjun Kim, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park
Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell. IEICE Trans. Electron. (5) (2016)
Sungjun Kim, Sunghun Jung, Min-Hwi Kim, Seongjae Cho, Byung-Gook Park
Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals. IEICE Trans. Electron. (5) (2015)
Mina Yun, Seongjae Cho, Sae-Kyoung Kang, Sunghun Jung, Byung-Gook Park
Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect. ISCE (2015)
Sung Yun Woo, Young Jun Yoon, Jae Hwa Seo, Gwan Min Yoo, Seongjae Cho, In Man Kang
InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate. IEICE Trans. Electron. (7) (2014)
Seongjae Cho, Sunghun Jung, Sungjun Kim, Byung-Gook Park
Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access. IEICE Electron. Express 11 (4) (2014)
Seongjae Cho, Hyungjin Kim, Min-Chul Sun, In Man Kang, Byung-Gook Park, James S. Harris Jr.
Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance. IEICE Electron. Express 9 (9) (2012)
Gil Sung Lee, Doo-Hyun Kim, Seongjae Cho, Byung-Gook Park
A New 1T DRAM Cell: Cone Type 1T DRAM Cell. IEICE Trans. Electron. (5) (2011)
Seongjae Cho, Jung Hoon Lee, Yoon Kim, Jang-Gn Yun, Hyungcheol Shin, Byung-Gook Park
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices. IEICE Trans. Electron. (5) (2010)
Dong-Seup Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jung Han Lee, Seongjae Cho, Byung-Gook Park
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer. IEICE Trans. Electron. (5) (2010)
Seongjae Cho, In Man Kang, Kyung Rok Kim
Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs. IEICE Electron. Express 7 (19) (2010)
Sang Hyuk Park, Sangwoo Kang, Seongjae Cho, Dong-Seup Lee, Jung Han Lee, Hong-Seon Yang, Kwon-Chil Kang, Joung-Eob Lee, Jong Duk Lee, Byung-Gook Park
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation. IEICE Trans. Electron. (5) (2009)
Yoon Kim, Seongjae Cho, Gil Sung Lee, Il-Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. IEICE Trans. Electron. (5) (2009)
Byung-Gook Park, Jae Young Song, Jong Pil Kim, Hoon Jeong, Jung Hoon Lee, Seongjae Cho
Nanosculpture: Three-dimensional CMOS device structures for the ULSI era. Microelectron. J. 40 (4-5) (2009)
Seongjae Cho, Jung Hoon Lee, Gil Sung Lee, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL). IEICE Trans. Electron. (5) (2009)
Doo-Hyun Kim, Il-Han Park, Seongjae Cho, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. IEICE Trans. Electron. (5) (2009)
Jang-Gn Yun, Il-Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. IEICE Trans. Electron. (5) (2008)
Seongjae Cho, Il-Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). IEICE Trans. Electron. (5) (2008)
Hochul Lee, Youngchang Yoon, Seongjae Cho, Hyungcheol Shin
Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs. IEICE Trans. Electron. (5) (2007)
Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park
Design and Simulation of Asymmetric MOSFETs. IEICE Trans. Electron. (5) (2007)
Seongjae Cho, Jang-Gn Yun, Il-Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. IEICE Trans. Electron. (5) (2007)