Sung-Yun Lee

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 11

Top Topics

State Abstraction

Logic Synthesis

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang
CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning. DATE (2024)
Daeyeon Kim, Sung-Yun Lee, Kyungjun Min, Seokhyeong Kang
Construction of Realistic Place-and-Route Benchmarks for Machine Learning Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (6) (2023)
Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang
ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks. ICCAD (2023)
Sung-Yun Lee, Seonghyeon Park, Daeyeon Kim, Minjae Kim, Tuyen P. Le, Seokhyeong Kang
RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization. DATE (2023)
Sung-Yun Lee, Daeyeon Kim, Kyungjun Min, Seokhyeong Kang
Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration. ASP-DAC (2022)
Daeyeon Kim, Hyun-jeong Kwon, Sung-Yun Lee, Seungwon Kim, Mingyu Woo, Seokhyeong Kang
Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator. DATE (2021)
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang
A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2020)
Hyun-jeong Kwon, Sung-Yun Lee, Young Hwan Kim, Seokhyeong Kang
Additive Statistical Leakage Analysis Using Exponential Mixture Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Daeyeon Kim, SangGi Do, Sung-Yun Lee, Seokhyeong Kang
Compact Topology-Aware Bus Routing for Design Regularity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (8) (2020)
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang
Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. ISMVL (2019)
Sung-Yun Lee, Sunmean Kim, Seokhyeong Kang
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm. ISMVL (2019)