Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic.

Sunmean Kim Sung-Yun Lee Sunghye Park Seokhyeong Kang

Published in: ISMVL (2019)

Keyphrases

logic circuits
low power
functional decomposition
logic synthesis
gate array
power consumption
case study
high speed
logic programming
design process
power dissipation
tunnel diode
image analysis
hidden markov models
edge detection
level set