Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction.
Kiyung KimSunmean KimYongsu LeeDaeyeon KimSo-Young KimSeokhyeong KangByoung Hun LeePublished in: ISMVL (2020)
Keyphrases
- low power
- logic circuits
- high speed
- gate array
- power dissipation
- cmos technology
- power consumption
- wireless transmission
- low cost
- energy dissipation
- nm technology
- power reduction
- high power
- digital signal processing
- functional decomposition
- single chip
- tunnel diode
- low power consumption
- signal processor
- real time
- delay insensitive
- vlsi circuits
- wireless networks
- computer vision