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Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology.
Dongyun Kam
Byeong Yong Kong
Youngjoo Lee
Published in:
VLSI Technology and Circuits (2022)
Keyphrases
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cmos technology
cost efficient
low power
low voltage
power consumption
parallel processing
spl times
turbo codes
silicon on insulator
low complexity
image sensor
power dissipation
mixed signal
software systems
real time
rate distortion
error concealment
image quality
high speed
motion estimation
computer vision