Charles Augustine

Publication Activity (10 Years)

Years Active: 1992-2023
Publications (10 Years): 31

Top Topics

Metal Oxide Semiconductor

Error Detection

Top Venues

IEEE J. Solid State Circuits

Publications

Charles Augustine, Hai Helen Li
ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-19. IEEE Des. Test 40 (1) (2023)
Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits (2023)
Charles Eckert, Arun Subramaniyan, Xiaowei Wang, Charles Augustine, Ravishankar Iyer, Reetuparna Das
Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. IEEE Trans. Computers 72 (6) (2023)
Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das
Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM (2021)
Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi Iyer, Li Zhao, Reetuparna Das
Cache Compression with Efficient in-SRAM Data Comparison. NAS (2021)
Charles Augustine, A. Afzal, U. Misgar, A. Owahid, A. Raman, K. Subramanian, Feroze Merchant, James W. Tschanz, Muhammad M. Khellah
All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP. VLSI Circuits (2021)
Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De
25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. ISSCC (2020)
Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits (2020)
Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De
A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response. IEEE J. Solid State Circuits 55 (4) (2020)
Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, R. Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, C. Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits (2020)
Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah, Vivek De
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. VLSI Circuits (2020)
Xiaowei Wang, Jiecao Yu, Charles Augustine, Ravi R. Iyer, Reetuparna Das
Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks. HPCA (2019)
Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54 (1) (2019)
Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De
A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response. VLSI Circuits (2019)
Bruno U. Pedroni, Sadique Sheik, Hesham Mostafa, Somnath Paul, Charles Augustine, Gert Cauwenberghs
Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting. BioCAS (2018)
Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC (2018)
Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits 52 (1) (2017)
Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs
Membrane-Dependent Neuromorphic Learning Rule for Unsupervised Spike Pattern Detection. CoRR (2017)
Georgios Detorakis, Sadique Sheik, Charles Augustine, Somnath Paul, Bruno U. Pedroni, Nikil D. Dutt, Jeffrey L. Krichmar, Gert Cauwenberghs, Emre Neftci
Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning. CoRR (2017)
Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis
Event-driven random backpropagation: Enabling neuromorphic deep learning machines. ISCAS (2017)
Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity. CoRR (2016)
Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE J. Solid State Circuits 51 (1) (2016)
Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC (2016)
Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs
Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection. BioCAS (2016)
Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
Cache Design with Domain Wall Memory. IEEE Trans. Computers 65 (4) (2016)
Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits 51 (1) (2016)
Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis
Event-driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines. CoRR (2016)
Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
Forward table-based presynaptic event-triggered spike-timing-dependent plasticity. BioCAS (2016)
Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah, Gert Cauwenberghs, Emre Neftci
Synaptic sampling in hardware spiking neural networks. ISCAS (2016)
Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ISSCC (2015)
Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC (2015)
Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC (2014)
Niladri Narayan Mojumder, Xuanyao Fong, Charles Augustine, Sumeet Kumar Gupta, Sri Harsha Choday, Kaushik Roy
Dual pillar spin-transfer torque MRAMs for low power applications. ACM J. Emerg. Technol. Comput. Syst. 9 (2) (2013)
Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz
Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED (2013)
Georgios Panagopoulos, Charles Augustine, Kaushik Roy
A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach. DATE (2012)
Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
Cognitive computing with spin-based neural networks. DAC (2012)
Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
Proposal For Neuromorphic Hardware Using Spin Devices CoRR (2012)
Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
Spin based neuron-synapse module for ultra low power programmable computational networks. IJCNN (2012)
Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
Ultra low energy analog image processing using spin based neurons. NANOARCH (2012)
Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED (2012)
Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan
Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH (2011)
Charles Augustine, Georgios Panagopoulos, Behtash Behin-Aein, Srikant Srinivasan, Angik Sarkar, Kaushik Roy
Low-power functionality enhanced computation architecture using spin-based devices. NANOARCH (2011)
Farshad Moradi, Charles Augustine, Ashish Goel, Georgios Karakonstantis, Tuan Vu Cao, Dag T. Wisland, Hamid Mahmoodi, Kaushik Roy
Data-dependant sense-amplifier flip-flop for low power applications. CICC (2010)
Georgios Karakonstantis, Charles Augustine, Kaushik Roy
A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique. IOLTS (2010)
Charles Augustine, Arijit Raychowdhury, Yunfei Gao, Mark S. Lundstrom, Kaushik Roy
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices. ISQED (2009)
Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy
A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. ASP-DAC (2009)
Jing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. DAC (2008)
Nilanjan Banerjee, Charles Augustine, Kaushik Roy
Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems. DFT (2008)
Louise Osterholtz, Charles Augustine, Arthur E. McNair, Ivica Rogina, Hiroaki Saito, Tilo Sloboda, Joe Tebelskis, Alex Waibel
Testing generality in JANUS: a multi-lingual speech translation system. ICASSP (1992)