Rangharajan Venkatesan

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 37

Top Topics

Jump Diffusion Process

Top Venues

IEEE Trans. Computers

Publications

Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz
Vision Transformer Computation and Resilience for Dynamic Inference. ISPASS (2024)
Steve Dai, Hasan Genc, Rangharajan Venkatesan, Brucek Khailany
Efficient Transformer Inference with Statically Structured Sparse Attention. DAC (2023)
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. IEEE J. Solid State Circuits 58 (4) (2023)
Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz
Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications. CoRR (2022)
Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. ICML (2022)
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Fayez Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. IEEE Trans. Computers 71 (12) (2022)
Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. CoRR (2022)
Geoffrey W. Burr, SukHwan Lim, Boris Murmann, Rangharajan Venkatesan, Marian Verhelst
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips. IEEE Des. Test 39 (3) (2022)
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany
A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. VLSI Technology and Circuits (2022)
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. CoRR (2021)
Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William J. Dally, Brucek Khailany
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. MLSys (2021)
Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. CoRR (2021)
Steve Dai, Alicia Klinefelter, Haoxing Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Ross Pinckney, Brucek Khailany
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. CoRR (2021)
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. DAC (2021)
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Ming-Yu Liu, Brucek Khailany, Bill Dally, Anima Anandkumar
Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update. CoRR (2021)
Nathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany
IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs. ICCAD (2021)
Thomas Burd, Rangharajan Venkatesan, Dennis Sylvester
Session 3 Overview: Highlighted Chip Releases: Modern Digital SoCs Invited Papers. ISSCC (2021)
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64 (6) (2021)
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55 (4) (2020)
Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally
Accelerating Chip Design With Machine Learning. IEEE Micro 40 (6) (2020)
Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer
Timeloop: A Systematic Approach to DNN Accelerator Evaluation. ISPASS (2019)
Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD (2019)
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits (2019)
Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray
Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. DAC (2019)
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO (2019)
Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. ASPLOS (2019)
Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium (2019)
Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer
A modular digital VLSI flow for high-productivity SoC design. DAC (2018)
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA (2017)
Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan
STAxCache: An approximate, energy efficient STT-MRAM cache. DATE (2017)
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR (2017)
Xuanyao Fong, Yusung Kim, Rangharajan Venkatesan, Sri Harsha Choday, Anand Raghunathan, Kaushik Roy
Spin-Transfer Torque Memories: Devices, Circuits, and Systems. Proc. IEEE 104 (7) (2016)
Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Stephen W. Keckler
A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications. DAC (2016)
Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Mrigank Sharad, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
Cache Design with Domain Wall Memory. IEEE Trans. Computers 65 (4) (2016)
Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey
Emulation-Based Analysis of System-on-Chip Performance Under Variations. IEEE Trans. Very Large Scale Integr. Syst. 24 (12) (2016)
A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes. ACM J. Emerg. Technol. Comput. Syst. 13 (2) (2016)
A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
Asymmetric underlapped FinFET based robust SRAM design at 7nm node. DATE (2015)
Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan
Spintastic: spin-based stochastic logic for energy-efficient computing. DATE (2015)
Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan
DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes. DATE (2015)
Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage. ACM J. Emerg. Technol. Comput. Syst. 12 (1) (2015)
Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing. ISLPED (2014)
Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. ISCA (2014)
Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes. DATE (2013)
Mrigank Sharad, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches. ISLPED (2013)
Mrigank Sharad, Rangharajan Venkatesan, Xuanyao Fong, Anand Raghunathan, Kaushik Roy
Reading spin-torque memory with spin-torque sensors. NANOARCH (2013)
Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan
TapeCache: a high density, energy efficient cache based on domain wall memory. ISLPED (2012)
Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey
VESPA: Variability emulation for System-on-Chip performance analysis. DATE (2011)
Rangharajan Venkatesan, Vinay K. Chippa, Charles Augustine, Kaushik Roy, Anand Raghunathan
Energy efficient many-core processor for recognition and mining using spin-based memory. NANOARCH (2011)
Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan
MACACO: Modeling and analysis of circuits for approximate computing. ICCAD (2011)