A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology.
Rangharajan VenkatesanYakun Sophia ShaoBrian ZimmerJason ClemonsMatthew FojtikNan JiangBen KellerAlicia KlinefelterNathaniel Ross PinckneyPriyanka RainaStephen G. TellYanqing ZhangWilliam J. DallyJoel S. EmerC. Thomas GrayStephen W. KecklerBrucek KhailanyPublished in: Hot Chips Symposium (2019)
Keyphrases
- neural network
- vlsi design
- high speed
- wide range
- chip design
- single chip
- host computer
- back propagation
- vlsi implementation
- neural network is trained
- design methodology
- network architecture
- analog vlsi
- parallel implementation
- neural nets
- recurrent neural networks
- self organizing maps
- fuzzy logic
- artificial neural networks
- genetic algorithm