Joel S. Emer

ORCID

Publication Activity (10 Years)

Years Active: 1984-2023
Publications (10 Years): 77

Top Venues

Publications

Michael Pellauer, Jason Clemons, Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Donghyuk Lee, Mike O'Connor, Anghsuman Parashar, Sean Treichler, Po-An Tsai, Stephen W. Keckler, Joel S. Emer
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing. ACM Trans. Comput. Syst. 41 (2023)
Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, Joel S. Emer, Daniel Sánchez
Accelerating RTL Simulation with Hardware-Software Co-Design. MICRO (2023)
Kyungmi Lee, Mengjia Yan, Joel S. Emer, Anantha P. Chandrakasan
SecureLoop: Design Space Exploration of Secure DNN Accelerators. MICRO (2023)
Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. CoRR (2023)
Yifan Yang, Joel S. Emer, Daniel Sánchez
ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining. HPCA (2023)
Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. ASPLOS (3) (2023)
Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract). HOPC@SPAA (2023)
Olivia Hsu, Maxwell Strange, Ritvik Sharma, Jaeyeon Won, Kunle Olukotun, Joel S. Emer, Mark A. Horowitz, Fredrik Kjølstad
The Sparse Abstract Machine. ASPLOS (3) (2023)
Weon Taek Na, Joel S. Emer, Mengjia Yan
Penetrating Shields: A Systematic Analysis of Memory Corruption Mitigations in the Spectre Era. CoRR (2023)
Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. MICRO (2023)
Peter W. Deutsch, Weon Taek Na, Thomas Bourgeat, Joel S. Emer, Mengjia Yan
Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes. ISCA (2023)
Tanner Andrulis, Joel S. Emer, Vivienne Sze
RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! CoRR (2023)
Jaeyeon Won, Charith Mendis, Joel S. Emer, Saman P. Amarasinghe
WACO: Learning Workload-Aware Co-optimization of the Format and Schedule of a Sparse Tensor Program. ASPLOS (2) (2023)
Yannan Nellie Wu, Po-An Tsai, Saurav Muralidharan, Angshuman Parashar, Vivienne Sze, Joel S. Emer
HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity. CoRR (2023)
Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. DCC (2023)
Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. MICRO (2023)
Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity. CoRR (2023)
Michael Gilbert, Yannan Nellie Wu, Angshuman Parashar, Vivienne Sze, Joel S. Emer
LoopTree: Enabling Exploration of Fused-layer Dataflow Accelerators. ISPASS (2023)
Tanner Andrulis, Joel S. Emer, Vivienne Sze
RAELLA: Reforming the Arithmetic for Efficient, Low-Resolution, and Low-Loss Analog PIM: No Retraining Required! ISCA (2023)
Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. HPEC (2023)
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. CoRR (2022)
Mark Horeni, Pooria Taheri, Po-An Tsai, Angshuman Parashar, Joel S. Emer, Siddharth Joshi
Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization. ISPASS (2022)
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
Sparseloop: An Analytical Approach To Sparse Tensor Accelerator Modeling. MICRO (2022)
Peter W. Deutsch, Yuheng Yang, Thomas Bourgeat, Jules Drean, Joel S. Emer, Mengjia Yan
DAGguise: mitigating memory timing side channels. ASPLOS (2022)
Olivia Hsu, Maxwell Strange, Jaeyeon Won, Ritvik Sharma, Kunle Olukotun, Joel S. Emer, Mark Horowitz, Fredrik Kjolstad
The Sparse Abstract Machine. CoRR (2022)
Yifan Yang, Joel S. Emer, Daniel Sánchez
SpZip: Architectural Support for Effective Data Compression In Irregular Applications. ISCA (2021)
Francis Wang, Yannan Nellie Wu, Matthew Woicik, Joel S. Emer, Vivienne Sze
Architecture-Level Energy Estimation for Heterogeneous Computing Systems. ISPASS (2021)
Guowei Zhang, Nithya Attaluri, Joel S. Emer, Daniel Sánchez
Gamma: leveraging Gustavson's algorithm to accelerate sparse matrix multiplication. ASPLOS (2021)
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM 64 (6) (2021)
Yannan Nellie Wu, Po-An Tsai, Angshuman Parashar, Vivienne Sze, Joel S. Emer
Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators. ISPASS (2021)
Yannan Nellie Wu, Vivienne Sze, Joel S. Emer
An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs. ISPASS (2020)
Thomas Bourgeat, Jules Drean, Yuheng Yang, Lillian Tsai, Joel S. Emer, Mengjia Yan
CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches. MICRO (2020)
Siva Kumar Sastry Hari, Paolo Rech, Timothy Tsai, Mark Stephenson, Arslan Zulfiqar, Michael B. Sullivan, Philip P. Shirvani, Paul Racunas, Joel S. Emer, Stephen W. Keckler
Estimating Silent Data Corruption Rates Using a Two-Level Model. CoRR (2020)
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits 55 (4) (2020)
Liane Bernstein, Alexander Sludds, Ryan Hamerly, Vivienne Sze, Joel S. Emer, Dirk Englund
Freely scalable and reconfigurable optical hardware for deep learning. CoRR (2020)
Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer
Timeloop: A Systematic Approach to DNN Accelerator Evaluation. ISPASS (2019)
Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD (2019)
Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits (2019)
Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
Accelergy: An Architecture-Level Energy Estimation Methodology for Accelerator Designs. ICCAD (2019)
Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO (2019)
Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
ExTensor: An Accelerator for Sparse Tensor Algebra. MICRO (2019)
Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. ASPLOS (2019)
Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer, Vivienne Sze
Eyeriss v2: A Flexible Accelerator for Emerging Deep Neural Networks on Mobile Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (2) (2019)
Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium (2019)
Vivienne Sze, Yu-Hsin Chen, Joel S. Emer, Amr Suleiman, Zhengdong Zhang
Hardware for machine learning: Challenges and opportunities. CICC (2018)
Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
Eyeriss v2: A Flexible and High-Performance Accelerator for Emerging Deep Neural Networks. CoRR (2018)
Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors. IACR Cryptol. ePrint Arch. 2018 (2018)
Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel S. Emer, Daniel Sánchez
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism. MICRO (2018)
Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer
A modular digital VLSI flow for high-productivity SoC design. DAC (2018)
Vladimir Kiriansky, Ilia A. Lebedev, Saman P. Amarasinghe, Srinivas Devadas, Joel S. Emer
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors. MICRO (2018)
Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer
Efficient Processing of Deep Neural Networks: A Tutorial and Survey. Proc. IEEE 105 (12) (2017)
Maleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey, Joel S. Emer, Daniel Sánchez
SAM: Optimizing Multithreaded Cores for Speculative Parallelism. PACT (2017)
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA (2017)
Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer
Automatic Construction of Program-Optimized FPGA Memory Networks. FPGA (2017)
Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel S. Emer, Daniel Sánchez
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism. ISCA (2017)
Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel S. Emer
Efficient Processing of Deep Neural Networks: A Tutorial and Survey. CoRR (2017)
Guanpeng Li, Siva Kumar Sastry Hari, Michael B. Sullivan, Timothy Tsai, Karthik Pattabiraman, Joel S. Emer, Stephen W. Keckler
Understanding error propagation in deep learning neural network (DNN) accelerators and applications. SC (2017)
Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators. IEEE Micro 37 (3) (2017)
Tien-Ju Yang, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
A method to estimate the energy consumption of deep neural networks. ACSSC (2017)
Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR (2017)
Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. IEEE J. Solid State Circuits 52 (1) (2017)
Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
Towards closing the energy gap between HOG and CNN features for embedded vision (Invited paper). ISCAS (2017)
Amr Suleiman, Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
Towards Closing the Energy Gap Between HOG and CNN Features for Embedded Vision. CoRR (2017)
Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Michael Adler, Joel S. Emer
(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies. ACM Trans. Reconfigurable Technol. Syst. 10 (2) (2017)
Siva Kumar Sastry Hari, Timothy Tsai, Mark Stephenson, Stephen W. Keckler, Joel S. Emer
SASSIFI: An architecture-level fault injection tool for GPU application resilience evaluation. ISPASS (2017)
Yu-Hsin Chen, Joel S. Emer, Vivienne Sze
Eyeriss: A Spatial Architecture for Energy-Efficient Dataflow for Convolutional Neural Networks. ISCA (2016)
Vivienne Sze, Yu-Hsin Chen, Joel S. Emer, Amr Suleiman, Zhengdong Zhang
Hardware for Machine Learning: Challenges and Opportunities. CoRR (2016)
Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Sánchez
Data-centric execution of speculative parallel programs. MICRO (2016)
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer
LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning. FPGA (2016)
Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez
Unlocking Ordered Parallelism with the Swarm Architecture. IEEE Micro 36 (3) (2016)
Aditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel S. Emer, Stephen W. Keckler
CLARA: Circular Linked-List Auto and Self Refresh Architecture. MEMSYS (2016)
Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze
14.5 Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. ISSCC (2016)
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Felix Winterstein, Joel S. Emer
Scavenger: Automating the construction of application-optimized memory hierarchies. FPL (2015)
Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez
A scalable architecture for ordered parallelism. MICRO (2015)
Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer
A fast and accurate analytical technique to compute the AVF of sequential bits in a processor. MICRO (2015)
Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel S. Emer
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches. HPCA (2015)
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33 (3) (2015)
Jesmin Jahan Tithi, Neal Clayton Crago, Joel S. Emer
Exploiting spatial architectures for edit distance algorithms. ISPASS (2014)
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34 (3) (2014)
Kermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer
The LEAP FPGA operating system. FPL (2014)
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer
LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories. FCCM (2014)
Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer
Optimizing under abstraction: Using prefetching to improve FPGA performance. FPL (2013)
Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer
Using in-flight chains to build a scalable cache coherence protocol. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA (2013)
Peng Li, Angshuman Parashar, Michael Pellauer, Tao Wang, Joel S. Emer
A Hierarchical Architectural Framework for Reconfigurable Logic Computing. IPDPS Workshops (2013)
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer
Scheduling heterogeneous multi-cores through performance impact estimation (PIE). ISCA (2012)
Aamer Jaleel, Hashem Hashemi Najaf-abadi, Samantika Subramaniam, Simon C. Steely Jr., Joel S. Emer
CRUISE: cache replacement and utility-aware scheduling. ASPLOS (2012)
Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer
Leveraging latency-insensitivity to ease multiple FPGA design. FPGA (2012)
William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon C. Steely Jr., Joel S. Emer
The gradient-based cache partitioning algorithm. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Sang Woo Jun, Kermin Fleming, Michael Adler, Joel S. Emer
ZIP-IO: Architecture for application-specific compression of Big Data. FPT (2012)
Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer
Leap scratchpads: automatic memory and cache management for reconfigurable logic. FPGA (2011)
Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. HPCA (2011)
Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer
PACMan: prefetch-aware cache management for high performance caching. MICRO (2011)
Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer
SHiP: signature-based hit predictor for high performance caching. MICRO (2011)
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer
High performance cache replacement using re-reference interval prediction (RRIP). ISCA (2010)
Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer
Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies. MICRO (2010)
Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer
Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). MEMOCODE (2010)
James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi
The Future of Architectural Simulation. IEEE Micro 30 (3) (2010)
Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang M. Yardi
CAMP: A technique to estimate per-structure power at run-time using a few simple parameters. HPCA (2009)
Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer
Soft connections: addressing the hardware-design modularity problem. DAC (2009)

Joel S. Emer.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Joel S. Emer