Daniel Lustig

Publication Activity (10 Years)

Years Active: 2011-2023
Publications (10 Years): 23

Top Topics

Maintaining Consistency

Abstraction Hierarchy

Memory Management

Top Venues

Publications

Harini Muthukrishnan, Daniel Lustig, Oreste Villa, Thomas F. Wenisch, David W. Nellans
FinePack: Transparently Improving the Efficiency of Fine-Grained Transfers in Multi-GPU Systems. HPCA (2023)
Vijay Kandiah, Daniel Lustig, Oreste Villa, David W. Nellans, Nikos Hardavellas
Parsimony: Enabling SIMD/Vector Programming in Standard Compiler Flows. CGO (2023)
Daniel Lustig, Simon Cooksey, Olivier Giroux
Mixed-proxy extensions for the NVIDIA PTX memory consistency model: industrial product. ISCA (2022)
Harini Muthukrishnan, David W. Nellans, Daniel Lustig, Jeffrey A. Fessler, Thomas F. Wenisch
Efficient Multi-GPU Shared Memory via Automatic Optimization of Fine-Grained Transfers. ISCA (2021)
Harini Muthukrishnan, Daniel Lustig, David W. Nellans, Thomas F. Wenisch
GPS: A Global Publish-Subscribe Model for Multi-GPU Memory Management. MICRO (2021)
Oreste Villa, Daniel Lustig, Zi Yan, Evgeny Bolotin, Yaosheng Fu, Niladrish Chatterjee, Nan Jiang, David W. Nellans
Need for Speed: Experiences Building a Trustworthy System-Level GPU Simulator. HPCA (2021)
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi
RealityCheck: Bringing Modularity, Hierarchy, and Abstraction to Automated Microarchitectural Memory Consistency Verification. CoRR (2020)
Xiaowei Ren, Daniel Lustig, Evgeny Bolotin, Aamer Jaleel, Oreste Villa, David W. Nellans
HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems. HPCA (2020)
Zi Yan, Daniel Lustig, David W. Nellans, Abhishek Bhattacharjee
Translation ranger: operating system support for contiguity-aware TLBs. ISCA (2019)
Zi Yan, Daniel Lustig, David W. Nellans, Abhishek Bhattacharjee
Nimble Page Management for Tiered Memory Systems. ASPLOS (2019)
Daniel Lustig, Sameer Sahasrabuddhe, Olivier Giroux
A Formal Analysis of the NVIDIA PTX Memory Consistency Model. ASPLOS (2019)
Caroline Trippel, Daniel Lustig, Margaret Martonosi
Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach. IEEE Micro 39 (3) (2019)
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
Full-Stack Memory Model Verification with TriCheck. IEEE Micro 38 (3) (2018)
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Aarti Gupta
PipeProof: Automated Memory Consistency Proofs for Microarchitectural Specifications. MICRO (2018)
Caroline Trippel, Daniel Lustig, Margaret Martonosi
CheckMate: Automated Synthesis of Hardware Exploits and Security Litmus Tests. MICRO (2018)
Caroline Trippel, Daniel Lustig, Margaret Martonosi
MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence Protocols. CoRR (2018)
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer
RTLcheck: verifying the memory consistency of RTL designs. MICRO (2017)
Daniel Lustig, Andrew Wright, Alexandros Papakonstantinou, Olivier Giroux
Automated Synthesis of Comprehensive Memory Model Litmus Test Suites. ASPLOS (2017)
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA. ASPLOS (2017)
Daniel Lustig, Geet Sethi, Abhishek Bhattacharjee, Margaret Martonosi
Transistency Models: Memory Ordering at the Hardware-OS Interface. IEEE Micro 37 (3) (2017)
Yatin A. Manerkar, Caroline Trippel, Daniel Lustig, Michael Pellauer, Margaret Martonosi
Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings. CoRR (2016)
Daniel Lustig, Geet Sethi, Margaret Martonosi, Abhishek Bhattacharjee
COATCheck: Verifying Memory Ordering at the Hardware-OS Interface. ASPLOS (2016)
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
Exploring the Trisection of Software, Hardware, and ISA in Memory Model Design. CoRR (2016)
Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures. ISCA (2015)
Daniel Lustig, Michael Pellauer, Margaret Martonosi
Verifying Correct Microarchitectural Enforcement of Memory Consistency Models. IEEE Micro 35 (3) (2015)
Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
CCICheck: using µhb graphs to verify the coherence-consistency interface. MICRO (2015)
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33 (3) (2015)
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34 (3) (2014)
Daniel Lustig, Michael Pellauer, Margaret Martonosi
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models. MICRO (2014)
Daniel Lustig, Margaret Martonosi
Reducing GPU offload latency via fine-grained CPU-GPU synchronization. HPCA (2013)
Daniel Lustig, Abhishek Bhattacharjee, Margaret Martonosi
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs. ACM Trans. Archit. Code Optim. 10 (1) (2013)
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA (2013)
Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi
Shared last-level TLBs for chip multiprocessors. HPCA (2011)