Michael Pellauer

ORCID

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 37

Top Venues

Massachusetts Institute of Technology, Cambridge, MA, USA (PHD)

Education History

Massachusetts Institute of Technology, Cambridge, MA, USA

PHD

Publications

Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators (Abstract). HOPC@SPAA (2024)
Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher
FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design. CoRR (2024)
Chakshu Moar, Michael Pellauer, Hyoukjun Kwon
Characterizing the Accuracy - Efficiency Trade-off of Low-rank Decomposition in Language Models. CoRR (2024)
Michael Pellauer, Jason Clemons, Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Donghyuk Lee, Mike O'Connor, Anghsuman Parashar, Sean Treichler, Po-An Tsai, Stephen W. Keckler, Joel S. Emer
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing. ACM Trans. Comput. Syst. 41 (2023)
Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. CoRR (2023)
Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. ASPLOS (3) (2023)
Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract). HOPC@SPAA (2023)
Raveesh Garg, Michael Pellauer, Sivasankaran Rajamanickam, Tushar Krishna
Exploiting Inter-Operation Data Reuse in Scientific Applications using GOGETA. CoRR (2023)
Francisco Muñoz-Martínez, Raveesh Garg, Michael Pellauer, José L. Abellán, Manuel E. Acacio, Tushar Krishna
Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. ASPLOS (3) (2023)
Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. DCC (2023)
Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators. MICRO (2023)
Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra. HPEC (2023)
Francisco Muñoz-Martínez, Raveesh Garg, José L. Abellán, Michael Pellauer, Manuel E. Acacio, Tushar Krishna
Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. CoRR (2023)
Prasanth Chatarasi, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Tushar Krishna, Vivek Sarkar
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators. ACM Trans. Archit. Code Optim. 19 (1) (2022)
Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators. DATE (2022)
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
A Formalism of DNN Accelerator Flexibility. SIGMETRICS (Abstracts) (2022)
Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators. CoRR (2022)
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
A Formalism of DNN Accelerator Flexibility. Proc. ACM Meas. Anal. Comput. Syst. 6 (2) (2022)
Eric Qin, Raveesh Garg, Abhimanyu Bambhaniya, Michael Pellauer, Angshuman Parashar, Sivasankaran Rajamanickam, Cong Hao, Tushar Krishna
Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity. CoRR (2022)
Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna
Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML. DAC (2022)
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
A Formalism of DNN Accelerator Flexibility. CoRR (2022)
Ananda Samajdar, Michael Pellauer, Tushar Krishna
Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration. CoRR (2021)
Hyoukjun Kwon, Liangzhen Lai, Michael Pellauer, Tushar Krishna, Yu-Hsin Chen, Vikas Chandra
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads. HPCA (2021)
Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
Flexion: A Quantitative Metric for Flexibility in DNN Accelerators. IEEE Comput. Archit. Lett. 20 (1) (2021)
Hyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, Tushar Krishna, Michael Pellauer, Angshuman Parashar
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings. IEEE Micro 40 (3) (2020)
Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach. MICRO (2019)
Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
ExTensor: An Accelerator for Sparse Tensor Algebra. MICRO (2019)
Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration. ASPLOS (2019)
Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition. ISCA (2018)
Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition. CoRR (2018)
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
Full-Stack Memory Model Verification with TriCheck. IEEE Micro 38 (3) (2018)
Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer
A modular digital VLSI flow for high-productivity SoC design. DAC (2018)
Hyoukjun Kwon, Michael Pellauer, Tushar Krishna
MAESTRO: An Open-source Infrastructure for Modeling Dataflows within Deep Learning Accelerators. CoRR (2018)
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer
RTLcheck: verifying the memory consistency of RTL designs. MICRO (2017)
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA. ASPLOS (2017)
Yatin A. Manerkar, Caroline Trippel, Daniel Lustig, Michael Pellauer, Margaret Martonosi
Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings. CoRR (2016)
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
Exploring the Trisection of Software, Hardware, and ISA in Memory Model Design. CoRR (2016)
Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures. ISCA (2015)
Daniel Lustig, Michael Pellauer, Margaret Martonosi
Verifying Correct Microarchitectural Enforcement of Memory Consistency Models. IEEE Micro 35 (3) (2015)
Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
CCICheck: using µhb graphs to verify the coherence-consistency interface. MICRO (2015)
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33 (3) (2015)
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34 (3) (2014)
Daniel Lustig, Michael Pellauer, Margaret Martonosi
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models. MICRO (2014)
Michel A. Kinsy, Michael Pellauer, Srinivas Devadas
Heracles: a tool for fast RTL-based design space exploration of multicore processors. FPGA (2013)
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA (2013)
Peng Li, Angshuman Parashar, Michael Pellauer, Tao Wang, Joel S. Emer
A Hierarchical Architectural Framework for Reconfigurable Logic Computing. IPDPS Workshops (2013)
Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer
Leveraging latency-insensitivity to ease multiple FPGA design. FPGA (2012)
Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer
Leap scratchpads: automatic memory and cache management for reconfigurable logic. FPGA (2011)
Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. HPCA (2011)
Michel A. Kinsy, Michael Pellauer, Srinivas Devadas
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System. FPL (2011)
Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer
Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). MEMOCODE (2010)
Nirav Dave, Man Cheuk Ng, Michael Pellauer, Arvind
A design flow based on modular refinement. MEMOCODE (2010)
Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer
Soft connections: addressing the hardware-design modularity problem. DAC (2009)
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2 (3) (2009)
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS (2008)
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA (2008)
Nirav Dave, Arvind, Michael Pellauer
Scheduling as Rule Composition. MEMOCODE (2007)
Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. MEMOCODE (2007)
Nirav Dave, Michael Pellauer, S. Gerding, Arvind
802.11a transmitter: a case study in microarchitectural exploration. MEMOCODE (2006)
Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil
Synthesis of synchronous assertions with guarded atomic actions. MEMOCODE (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Michael Pellauer