Muralidaran Vijayaraghavan

Publication Activity (10 Years)

Years Active: 2007-2018
Publications (10 Years): 10

Top Venues

CoRR

MEMOCODE

Proc. ACM Program. Lang.

PACT

Massachusetts Institute of Technology, Cambridge, USA (PHD)

Education History

Massachusetts Institute of Technology, Cambridge, USA

PHD

Publications

Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind
Constructing a Weak Memory Model. ISCA (2018)
Sizhuo Zhang, Muralidaran Vijayaraghavan, Andrew Wright, Mehdi Alipour, Arvind
Constructing a Weak Memory Model. CoRR (2018)
Joonwon Choi, Muralidaran Vijayaraghavan, Benjamin Sherman, Adam Chlipala, Arvind
Kami: a platform for high-level parametric hardware specification and its modular verification. Proc. ACM Program. Lang. 1 (ICFP) (2017)
Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
An Operational Framework for Specifying Memory Models using Instantaneous Instruction Execution. CoRR (2017)
Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility. CoRR (2017)
Sizhuo Zhang, Muralidaran Vijayaraghavan, Arvind
Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility. PACT (2017)
Sizhuo Zhang, Muralidaran Vijayaraghavan, Dan Lustig, Arvind
Weak Memory Models with Matching Axiomatic and Operational Definitions. CoRR (2017)
Sizhuo Zhang, Arvind, Muralidaran Vijayaraghavan
Taming Weak Memory Models. CoRR (2016)
Muralidaran Vijayaraghavan, Adam Chlipala, Arvind, Nirav Dave
Modular Deductive Verification of Multiprocessor Hardware Designs. CAV (2) (2015)
Xiangyao Yu, Muralidaran Vijayaraghavan, Srinivas Devadas
A Proof of Correctness for the Tardis Cache Coherence Protocol. CoRR (2015)
Michal Karczmarek, Arvind, Muralidaran Vijayaraghavan
A new synthesis procedure for atomic rules containing multi-cycle function blocks. MEMOCODE (2014)
Muralidaran Vijayaraghavan, Nirav Dave, Arvind
Modular compilation of guarded atomic actions. MEMOCODE (2013)
Asif Khan, Muralidaran Vijayaraghavan, Arvind
A general technique for deterministic model-cycle-level debugging. MEMOCODE (2012)
Asif Khan, Muralidaran Vijayaraghavan, Silas Boyd-Wickizer, Arvind
Fast and cycle-accurate modeling of a multicore processor. ISPASS (2012)
Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer
Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID). MEMOCODE (2010)
Muralidaran Vijayaraghavan, Arvind
Bounded Dataflow Networks and Latency-Insensitive circuits. MEMOCODE (2009)
Abhinav Agarwal, Nirav Dave, Kermin Fleming, Asif Khan, Myron King, Man Cheuk Ng, Muralidaran Vijayaraghavan
Implementing a fast cartesian-polar matrix interpolator. MEMOCODE (2009)
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2 (3) (2009)
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS (2008)
Kermin Fleming, Myron King, Man Cheuk Ng, Asif Khan, Muralidaran Vijayaraghavan
High-throughput Pipelined Mergesort. MEMOCODE (2008)
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA (2008)
Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA. MEMOCODE (2007)
Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Dave, Arvind, Gopal Raghavan, Jamey Hicks
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols. MEMOCODE (2007)

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Publication Activity (10 Years)

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Muralidaran Vijayaraghavan