Manuel E. Acacio

ORCID

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 35

Top Venues

J. Supercomput.

IEEE Trans. Parallel Distributed Syst.

CoRR

J. Parallel Distributed Comput.

Publications

Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
On the interactions between ILP and TLP with hardware transactional memory. Microprocess. Microsystems 104 (2024)
Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
Speculative inter-thread store-to-load forwarding in SMT architectures. J. Parallel Distributed Comput. 173 (2023)
Francisco Muñoz-Martínez, Raveesh Garg, Michael Pellauer, José L. Abellán, Manuel E. Acacio, Tushar Krishna
Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. ASPLOS (3) (2023)
Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators. ACM J. Emerg. Technol. Comput. Syst. 19 (4) (2023)
Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros
CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions. PACT (2023)
Francisco Muñoz-Martínez, Raveesh Garg, José L. Abellán, Michael Pellauer, Manuel E. Acacio, Tushar Krishna
Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. CoRR (2023)
Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna
Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators. IPDPS (2022)
J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 33 (1) (2022)
Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean
Analysing software prefetching opportunities in hardware transactional memory. J. Supercomput. 78 (1) (2022)
Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. PDP (2022)
Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna
A Taxonomy for Classification and Comparison of Dataflows for GNN Accelerators. CoRR (2021)
Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading. MICRO (2021)
Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators. IISWC (2021)
Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators. NOCS (2021)
Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators. IEEE Comput. Archit. Lett. 20 (2) (2021)
J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. J. Parallel Distributed Comput. 145 (2020)
Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
STONNE: A Detailed Architectural Simulator for Flexible Neural Network Accelerators. CoRR (2020)
J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 31 (6) (2020)
Manuel E. Acacio, Julio Sahuquillo
Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems. Concurr. Comput. Pract. Exp. 31 (21) (2019)
Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio
InsideNet: A tool for characterizing convolutional neural networks. Future Gener. Comput. Syst. 100 (2019)
Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio
CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators. Euro-Par Workshops (2019)
J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio
Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. 30 (11) (2019)
Gregorio Bernabé, Raúl Hernández, Manuel E. Acacio
Parallel implementations of the 3D fast wavelet transform on a Raspberry Pi 2 cluster. J. Supercomput. 74 (4) (2018)
José L. Abellán, Eduardo Padierna, Alberto Ros, Manuel E. Acacio
Photonic-based express coherence notifications for many-core CMPs. J. Parallel Distributed Comput. 113 (2018)
Gregorio Bernabé, Manuel E. Acacio
On the Parallelization of Stream Compaction on a Low-Cost SDC Cluster. Sci. Program. 2018 (2018)
Francisco Muñoz-Martínez, Manuel E. Acacio
SAWS: Simple and Adaptive Warp Scheduling for Improved Performance in Throughput Processors. PDP (2018)
J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS (2017)
Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. J. Supercomput. 73 (10) (2017)
Juan M. Cebrian, Ricardo Fernández Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros
A dedicated private-shared cache design for scalable multiprocessors. Concurr. Comput. Pract. Exp. 29 (2) (2017)
Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. ARCS (2016)
Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. J. Supercomput. 72 (2) (2016)
Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García
Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses. IEEE Trans. Computers 64 (6) (2015)
Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio
Fast and efficient commits for Lazy-Lazy hardware transactional memory. J. Supercomput. 71 (12) (2015)
Alberto Ros, Manuel E. Acacio
DASC-DIR: a low-overhead coherence directory for many-core processors. J. Supercomput. 71 (3) (2015)
Juan M. Cebrian, Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio
Early Experiences with Separate Caches for Private and Shared Data. e-Science (2015)
Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio
Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. Euro-Par Workshops (2) (2014)
Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio
Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems. J. Supercomput. 68 (2) (2014)
J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 25 (5) (2014)
Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio, Juan Fernández
Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory. ARCS (2013)
José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio
Efficient Dir0B Cache Coherency for Many-Core CMPs. ICCS (2013)
J. Rubén Titos Gil, Manuel E. Acacio, José M. García
Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24 (1) (2013)
José L. Abellán, Juan Fernández, Manuel E. Acacio
Design of an efficient communication infrastructure for highly contended locks in many-core CMPs. J. Parallel Distributed Comput. 73 (7) (2013)
J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24 (11) (2013)
José L. Abellán, Alberto Ros, Juan Fernández Peinador, Manuel E. Acacio
ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs. ICSAMOS (2013)
Mario Lodde, José Flich, Manuel E. Acacio
Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support. Euro-Par (2013)
Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio
On the design of energy-efficient hardware transactional memory systems. Concurr. Comput. Pract. Exp. 25 (6) (2013)
Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio
Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. SBAC-PAD (2012)
Manuel E. Acacio, Javier Cuenca, Lorenzo Fernández Maimó, Ricardo Fernández Pascual, Joaquín Cervera, Domingo Giménez, M. Carmen Garrido, Juan A. Sánchez-Laguna, José Guillén, Juan Alejandro Palomino Benito, María-Eugenia Requena
An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain. IPDPS Workshops (2012)
José L. Abellán, Juan Fernández Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs. DATE (2012)
José L. Abellán, Juan Fernández, Manuel E. Acacio
Efficient Hardware Barrier Synchronization in Many-Core CMPs. IEEE Trans. Parallel Distributed Syst. 23 (8) (2012)
Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García
ASCIB: adaptive selection of cache indexing bits for removing conflict misses. ISLPED (2012)
Mario Lodde, Jose Flich, Manuel E. Acacio
Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support. NOCS (2012)
Alberto Ros, Blas Cuesta Saez, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato
Extending Magny-Cours Cache Coherence. IEEE Trans. Computers 61 (5) (2012)
José M. Cecilia, José L. Abellán, Juan Fernández, Manuel E. Acacio, José M. García, Manuel Ujaldon
Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE. J. Supercomput. 62 (2) (2012)
J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
Hardware transactional memory with software-defined conflicts. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Manuel E. Acacio, Juan Fernández
Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems. PDP (2012)
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA (2012)
Mario Lodde, Jose Flich, Manuel E. Acacio
Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols. Euro-Par (2012)
J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS (2011)
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops (2011)
José L. Abellán, Juan Fernández, Manuel E. Acacio
GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs. IPDPS (2011)
Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT (2011)
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP (2011)
Antonio Flores, Manuel E. Acacio, Juan L. Aragón
Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs. J. Syst. Archit. 56 (9) (2010)
José L. Abellán, Juan Fernández, Manuel E. Acacio
Efficient and scalable barrier synchronization for many-core CMPs. Conf. Computing Frontiers (2010)
Antonio Flores, Juan L. Aragón, Manuel E. Acacio
Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs. IEEE Trans. Computers 59 (1) (2010)
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level. IEEE Trans. Parallel Distributed Syst. 21 (8) (2010)
Antonio Flores, Juan L. Aragón, Manuel E. Acacio
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. PDP (2010)
Alberto Ros, Manuel E. Acacio, José M. García
A scalable organization for distributed directories. J. Syst. Archit. 56 (2-3) (2010)
José L. Abellán, Juan Fernández, Manuel E. Acacio
Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats. J. Supercomput. 53 (2) (2010)
Alberto Ros, Blas Cuesta, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato
: Extending Magny-Cours coherence for large-scale servers. HiPC (2010)
Alberto Ros, Manuel E. Acacio
Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. Euro-Par Workshops (2010)
Alberto Ros, Manuel E. Acacio, José M. García
A Direct Coherence Protocol for Many-Core Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. 21 (12) (2010)
José L. Abellán, Juan Fernández, Manuel E. Acacio
A G-Line-Based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs. ICPP (2010)
Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio
Characterizing Energy Consumption in Hardware Transactional Memory Systems. SBAC-PAD (2010)
J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco
Speculation-based conflict resolution in hardware transactional memory. IPDPS (2009)
Joaquín Franco, Gregorio Bernabé, Juan Fernández, Manuel E. Acacio
A Parallel Implementation of the 2D Wavelet Transform Using CUDA. PDP (2009)
Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García
Distance-aware round-robin mapping for large NUCA caches. HiPC (2009)
Alberto Ros, Manuel E. Acacio, José M. García
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. APPT (2009)
Epifanio Gaona-Ramírez, Juan Fernández, Manuel E. Acacio
Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades. Euro-Par (2009)
Juan Fernández, Manuel E. Acacio, Gregorio Bernabé, José L. Abellán, Joaquín Franco
Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla. CSC (2008)
Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio, José M. García
Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distributed Comput. 68 (11) (2008)
Antonio Flores, Juan L. Aragón, Manuel E. Acacio
An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. J. Supercomput. 45 (3) (2008)
José L. Abellán, Juan Fernández, Manuel E. Acacio
Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades. ICCS (1) (2008)
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato
A fault-tolerant directory-based cache coherence protocol for CMP architectures. DSN (2008)
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures. IEEE Trans. Parallel Distributed Syst. 19 (8) (2008)
Alberto Ros, Manuel E. Acacio, José M. García
Scalable Directory Organization for Tiled CMP Architectures. CDES (2008)
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato
Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. HiPC (2008)
Alberto Ros, Manuel E. Acacio, José M. García
DiCo-CMP: Efficient cache coherency in tiled CMP architectures. IPDPS (2008)
J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco
Characterization of Conflicts in Log-Based Transactional Memory (LogTM). PDP (2008)
Antonio Flores, Manuel E. Acacio, Juan L. Aragón
Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. ICPP (2008)
J. Rubén Titos Gil, Manuel E. Acacio, José M. García
Directory-Based Conflict Detection in Hardware Transactional Memory. HiPC (2008)
José L. Abellán, Juan Fernández, Manuel E. Acacio
CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE. PDP (2008)
Antonio Flores, Juan L. Aragón, Manuel E. Acacio
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. AINA Workshops (1) (2007)
Alberto Ros, Manuel E. Acacio, José M. García
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. HiPC (2007)
Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. HPCA (2007)
Gregorio Bernabé, Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José González
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. Parallel Comput. 33 (1) (2007)
Antonio Flores, Juan L. Aragón, Manuel E. Acacio
Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. HiPC (2007)
Alberto Ros, Manuel E. Acacio, José M. García
An efficient cache design for scalable glueless shared-memory multiprocessors. Conf. Computing Frontiers (2006)
Francisco J. Villa, Manuel E. Acacio, José M. García
On the Evaluation of Dense Chip-Multiprocessor Architectures. ICSAMOS (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Manuel E. Acacio