Anurag Negi

Publication Activity (10 Years)

Years Active: 2010-2014
Publications (10 Years): 0

Top Topics

Parallel Architectures

Speculative Execution

Top Venues

ACM Trans. Archit. Code Optim.

IEEE Trans. Parallel Distributed Syst.

Publications

Bhavishya Goel, J. Rubén Titos Gil, Anurag Negi, Sally A. McKee, Per Stenström
Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell. IPDPS (2014)
J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 25 (5) (2014)
Madhavan Manivannan, Anurag Negi, Per Stenström
Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. ICPP (2013)
Anurag Negi, J. Rubén Titos Gil
SCIN-cache: Fast speculative versioning in multithreaded cores. ACM Trans. Archit. Code Optim. 9 (4) (2013)
Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal
Techniques to improve performance in requester-wins hardware transactional memory. ACM Trans. Archit. Code Optim. 10 (4) (2013)
J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24 (11) (2013)
Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, Tim Harris
HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. HiPC (2013)
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA (2012)
Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström
Transactional prefetching: narrowing the window of contention in hardware transactional memory. PACT (2012)
J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS (2011)
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops (2011)
Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT (2011)
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP (2011)
Anurag Negi, M. M. Waliullah, Per Stenström
LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems. IFMT (2010)
Anurag Negi, M. M. Waliullah, Per Stenström
: A low complexity lazy versioning HTM infrastructure. ICSAMOS (2010)