Madhavan Manivannan

ORCID

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 28

Top Venues

CoRR

ACM Trans. Archit. Code Optim.

IPDPS

DATE

Chalmers University of Technology, Gothenburg, Sweden (PHD)

Education History

Chalmers University of Technology, Gothenburg, Sweden

PHD

Publications

Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs. IPDPS (2024)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. EuroS&P (2023)
Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem. CF (2023)
Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. CoRR (2023)
Muhammad Waqar Azhar, Madhavan Manivannan, Per Stenström
Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints. ACM Trans. Archit. Code Optim. 20 (3) (2023)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
SCALE: Secure and Scalable Cache Partitioning. HOST (2023)
Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs
JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. ICPP (2023)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations. CoRR (2022)
Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, Miquel Pericàs
STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures. SBAC-PAD (2022)
Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, Miquel Pericàs
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. ACM Trans. Archit. Code Optim. 19 (2) (2022)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications. ACM Trans. Archit. Code Optim. 19 (2) (2022)
Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, Miquel Pericàs
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. CoRR (2022)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. CoRR (2021)
Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. PACT (2021)
Nadja Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs
DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors. IPDPS (2020)
Jing Chen, Pirah Noor Soomro, Mustafa Abduljabbar, Madhavan Manivannan, Miquel Pericàs
Scheduling Task-parallel Applications in Dynamically Asymmetric Environments. CoRR (2020)
Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, Seyed Saber Nabavi Larimi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, K. Mika, A. Hüffmeier, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. DATE (2020)
Jing Chen, Pirah Noor Soomro, Mustafa Abduljabbar, Madhavan Manivannan, Miquel Pericàs
Scheduling Task-parallel Applications in Dynamically Asymmetric Environments. ICPP Workshops (2020)
Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck
Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading. DAC (2020)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems. J. Parallel Distributed Comput. 144 (2020)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. IPDPS (2020)
Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck
Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading. DATE (2020)
Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, S. Nabavi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, D. Odman, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, K. Mika, A. Hüffmeier, Th. Jungeblu, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. CoRR (2019)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. CoRR (2019)
Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström
Coordinated Management of DVFS and Cache Partitioning under QoS Constraints to Save Energy in Multi-Core Systems. CoRR (2019)
Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
Global Dead-Block Management for Task-Parallel Programs. ACM Trans. Archit. Code Optim. 15 (3) (2018)
Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström
Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. IEEE Comput. Archit. Lett. 16 (2) (2017)
Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström
RADAR: Runtime-assisted dead region management for last-level caches. HPCA (2016)
Madhavan Manivannan, Per Stenström
Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures. IPDPS (2014)
Madhavan Manivannan, Anurag Negi, Per Stenström
Efficient Forwarding of Producer-Consumer Data in Task-Based Programs. ICPP (2013)
Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström
Implications of Merging Phases on Scalability of Multi-core Architectures. ICPP (2011)
Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström
Poster: implications of merging phases on scalability of multi-core architectures. ICS (2011)
Nagarajan Venkateswaran, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan, T. P. Ramnath Sai Sagar, Madhavan Manivannan, Sriram Murali, Vinoth Krishnan Elangovan
Towards modeling and integrated design automation of supercomputing clusters (MIDAS). Comput. Sci. Res. Dev. 24 (1-2) (2009)
Nagarajan Venkateswaran, Vinoth Krishnan Elangovan, Karthik Ganesan, T. R. S. Sagar, S. Aananthakrishanan, S. Ramalingam, Shyamsundar Gopalakrishnan, Madhavan Manivannan, Deepak Srinivasan, Viswanath Krishnamurthy, Karthik Chandrasekar, Viswanath Venkatesan, Balaji Subramaniam, V. Sangkar, Aravind Vasudevan, Shrikanth Ganapathy, Sriram Murali, M. Thyagarajan
On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system. IPDPS (2008)
Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Karthik Chandrasekar, Prem Kumar Ramesh, Viswanath Venkatesan, Arvindakshan Babu, Sudharshan
Future generation supercomputers I: a paradigm for node architecture. SIGARCH Comput. Archit. News 35 (5) (2007)
Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krishnamurthy, Sivaramakrishnan
Future generation supercomputers II: a paradigm for cluster architecture. SIGARCH Comput. Archit. News 35 (5) (2007)

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Publication Activity (10 Years)

Top Topics

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Madhavan Manivannan