Daniel A. Jiménez

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 36

Top Topics

Top Venues

Publications

Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas
A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering. CoRR (2024)
Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas
Practically Tackling Memory Bottlenecks of Graph-Processing Workloads. IPDPS (2024)
Alexandre Valentin Jamet, Georgios Vavouliotis, Daniel A. Jiménez, Lluc Alvarez, Marc Casas
A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering. HPCA (2024)
Josué Feliu, Arthur Perais, Daniel A. Jiménez, Alberto Ros
Rebasing Microarchitectural Research with Industry Traces. IISWC (2023)
Daniel A. Jiménez, Elvira Teran, Paul V. Gratz
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching. IEEE Comput. Archit. Lett. 22 (1) (2023)
Gino Chacon, Nathan Gober, Krishnendra Nathella, Paul V. Gratz, Daniel A. Jiménez
A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end. ISPASS (2023)
Nathan Gober, Gino Chacon, Lei Wang, Paul V. Gratz, Daniel A. Jiménez, Elvira Teran, Seth H. Pugsley, Jinchun Kim
The Championship Simulator: Architectural Simulation for Education and Competition. CoRR (2022)
Georgios Vavouliotis, Gino Chacon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jiménez, Marc Casas
Page Size Aware Cache Prefetching. MICRO (2022)
Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul V. Gratz, Daniel A. Jiménez, Samira Mirbagher Ajorpaz
Composite Instruction Prefetching. ICCD (2022)
Shixin Song, Tanvir Ahmed Khan, Sara Mahdizadeh-Shahri, Akshitha Sriraman, Niranjan K. Soundararajan, Sreenivas Subramoney, Daniel A. Jiménez, Heiner Litz, Baris Kasikci
Thermometer: profile-guided btb replacement for data center applications. ISCA (2022)
Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez
SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches. ICCD (2022)
Brady Testa, Samira Mirbagher Ajorpaz, Daniel A. Jiménez
Dynamic Set Stealing to Improve Cache Performance. SBAC-PAD (2022)
Tanvir Ahmed Khan, Muhammed Ugur, Krishnendra Nathella, Dam Sunwoo, Heiner Litz, Daniel A. Jiménez, Baris Kasikci
Whisper: Profile-Guided Branch Misprediction Elimination for Data Center Applications. MICRO (2022)
Georgios Vavouliotis, Lluc Alvarez, Boris Grot, Daniel A. Jiménez, Marc Casas
Morrigan: A Composite Instruction TLB Prefetcher. MICRO (2021)
Georgios Vavouliotis, Lluc Alvarez, Vasileios Karakostas, Konstantinos Nikas, Nectarios Koziris, Daniel A. Jiménez, Marc Casas
Exploiting Page Table Locality for Agile TLB Prefetching. ISCA (2021)
Daniel A. Jiménez
Top Picks From the 2020 Computer Architecture Conferences. IEEE Micro 41 (3) (2021)
Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, Seyed Saber Nabavi Larimi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, K. Mika, A. Hüffmeier, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. DATE (2020)
Brian Grayson, Jeff Rupley, Gerald D. Zuraski, Eric Quinnell, Daniel A. Jiménez, Tarun Nakra, Paul Kitchin, Ryan Hensley, Edward Brekelbaum, Vikas Sinha, Ankit Ghiya
Evolution of the Samsung Exynos CPU Microarchitecture. ISCA (2020)
Alexandre Valentin Jamet, Lluc Alvarez, Daniel A. Jiménez, Marc Casas
Characterizing the impact of last-level cache replacement policies on big-data workloads. IISWC (2020)
Samira Mirbagher Ajorpaz, Elba Garza, Gilles Pokam, Daniel A. Jiménez
CHiRP: Control-Flow History Reuse Prediction. MICRO (2020)
Samira Mirbagher Ajorpaz, Gilles Pokam, Esmaeil Mohammadian Koruyeh, Elba Garza, Nael B. Abu-Ghazaleh, Daniel A. Jiménez
PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron. MICRO (2020)
Daniel A. Jiménez
Support for Diverse Students. KDD (2020)
Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez
SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors. ICS (2020)
Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, S. Nabavi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, D. Odman, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, K. Mika, A. Hüffmeier, Th. Jungeblu, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. CoRR (2019)
Luna Backes, Daniel A. Jiménez
The impact of cache inclusion policies on cache management techniques. MEMSYS (2019)
Elba Garza, Samira Mirbagher Ajorpaz, Tahsin Ahmad Khan, Daniel A. Jiménez
Bit-level perceptron prediction for indirect branches. ISCA (2019)
Eshan Bhatia, Gino Chacon, Seth H. Pugsley, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez
Perceptron-based prefetch filtering. ISCA (2019)
Elvira Teran, Zeshan Chishti, Zhe Wang, Chris Wilkerson, Daniel A. Jiménez
Flexible associativity for DRAM caches. CF (2018)
Samira Mirbagher Ajorpaz, Elba Garza, Sangam Jindal, Daniel A. Jiménez
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer. ISCA (2018)
Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez
MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. IEEE Comput. Archit. Lett. 17 (2) (2018)
Jinchun Kim, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez, Seth H. Pugsley, Chris Wilkerson
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. ASPLOS (2017)
Daniel A. Jiménez, Elvira Teran
Multiperspective reuse prediction. MICRO (2017)
Elvira Teran, Zhe Wang, Daniel A. Jiménez
Perceptron learning for reuse prediction. MICRO (2016)
Qixiao Liu, Miquel Moretó, Jaume Abella, Francisco J. Cazorla, Daniel A. Jiménez, Mateo Valero
Sensible Energy Accounting with Abstract Metering for Multicore Systems. ACM Trans. Archit. Code Optim. 12 (4) (2016)
Zhe Wang, Daniel A. Jiménez, Tao Zhang, Gabriel H. Loh, Yuan Xie
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. SBAC-PAD (2016)
Elvira Teran, Yingying Tian, Zhe Wang, Daniel A. Jiménez
Minimal disturbance placement and promotion. HPCA (2016)
Yingying Tian, Sooraj Puthoor, Joseph L. Greathouse, Bradford M. Beckmann, Daniel A. Jiménez
Adaptive GPU cache bypassing. GPGPU@PPoPP (2015)
David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, Daniel A. Jiménez
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors. MICRO (2014)
Zhe Wang, Daniel A. Jiménez, Cong Xu, Guangyu Sun, Yuan Xie
Adaptive placement and migration policy for an STT-RAM-based hybrid cache. HPCA (2014)
Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez, Gabriel H. Loh
Last-level cache deduplication. ICS (2014)
Hyungjun Kim, Boris Grot, Paul V. Gratz, Daniel A. Jiménez
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. IEEE Trans. Computers 63 (3) (2014)
Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Onur Mutlu, Daniel A. Jiménez
Improving cache performance using read-write partitioning. HPCA (2014)
Samira Manabi Khan, Alaa R. Alameldeen, Chris Wilkerson, Jaydeep Kulkarni, Daniel A. Jiménez
Improving multi-core performance using mixed-cell cache architecture. HPCA (2013)
Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez
WADE: Writeback-aware dynamic cache management for NVM-based main memory system. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez
Temporal-based multilevel correlating inclusive cache replacement. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Daniel A. Jiménez
Insertion and promotion for tree-based PseudoLRU last-level caches. MICRO (2013)
Reena Panda, Paul V. Gratz, Daniel A. Jiménez
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors. IEEE Comput. Archit. Lett. 11 (2) (2012)
Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez
Improving writeback efficiency with decoupled last-write prediction. ISCA (2012)
Zhe Wang, Samira Manabi Khan, Daniel A. Jiménez
Rank idle time prediction driven last-level cache writeback. MSPC (2012)
Samira Manabi Khan, Zhe Wang, Daniel A. Jiménez
Decoupled dynamic cache segmentation. HPCA (2012)
Daniel A. Jiménez
An optimized scaled neural branch predictor. ICCD (2011)
Zhe Wang, Daniel A. Jiménez
Exploiting Rank Idle Time for Scheduling Last-Level Cache Writeback. PACT (2011)
Zhe Wang, Daniel A. Jiménez
Program Interferometry. PACT (2011)
Yingying Tian, Daniel A. Jiménez
Sampling Temporal Touch Hint (STTH) Inclusive Cache Management Policy. PACT (2011)
Zhe Wang, Daniel A. Jiménez
Program Interferometry. IISWC (2011)
Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz, Daniel A. Jiménez
Reducing network-on-chip energy consumption through spatial locality speculation. NOCS (2011)
Samira Manabi Khan, Daniel A. Jiménez
Decoupled Cache Segmentation: Mutable Policy with Automated Bypass. PACT (2011)
Samira Manabi Khan, Daniel A. Jiménez
Insertion policy selection using Decision Tree Analysis. ICCD (2010)
Samira Manabi Khan, Yingying Tian, Daniel A. Jiménez
Sampling Dead Block Prediction for Last-Level Caches. MICRO (2010)
Samira Manabi Khan, Daniel A. Jiménez, Doug Burger, Babak Falsafi
Using dead blocks as a virtual victim cache. PACT (2010)
Daniel A. Jiménez
Composite Confidence Estimators for Enhanced Speculation Control. SBAC-PAD (2009)
Renée St. Amant, Daniel A. Jiménez, Doug Burger
Mixed-Signal Approximate Computation: A Neural Predictor Case Study. IEEE Micro 29 (1) (2009)
Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization. Trans. High Perform. Embed. Archit. Compil. 2 (2009)
Daniel A. Jiménez
Generalizing neural branch prediction. ACM Trans. Archit. Code Optim. 5 (4) (2009)
Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, Mateo Valero
A Two-Level Load/Store Queue Based on Execution Locality. ISCA (2008)
Gabriel H. Loh, Daniel A. Jiménez
Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors. Int. J. Parallel Program. 36 (2) (2008)
Renée St. Amant, Daniel A. Jiménez, Doug Burger
Low-power, high-performance analog neural branch prediction. MICRO (2008)
Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
An evaluation infrastructure for power and energy optimisations. Int. J. Embed. Syst. 3 (1/2) (2007)
Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Daniel A. Jiménez, Mateo Valero
A Flexible Heterogeneous Multi-Core Architecture. PACT (2007)
Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
Efficient Program Power Behavior Characterization. HiPEAC (2007)
Daniel A. Jiménez
Guest Editor's Introduction. J. Instr. Level Parallelism 9 (2007)
Daniel A. Jiménez, Gabriel H. Loh
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. SBAC-PAD (2006)
Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero
A decoupled KILO-instruction processor. HPCA (2006)
Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
Toward an Evaluation Infrastructure for Power and Energy Optimizations. IPDPS (2005)
Daniel A. Jiménez
Piecewise Linear Branch Prediction. ISCA (2005)
Daniel A. Jiménez
Idealized Piecewise Linear Branch Prediction. J. Instr. Level Parallelism 7 (2005)
Chunling Hu, John B. P. McCabe, Daniel A. Jiménez, Ulrich Kremer
The Camino Compiler infrastructure. SIGARCH Comput. Archit. News 33 (5) (2005)
Daniel A. Jiménez
Code placement for improving dynamic branch prediction accuracy. PLDI (2005)
Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez, Mateo Valero
Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. ISHPC (2005)
Miquel Pericàs, Adrián Cristal, Rubén González, Daniel A. Jiménez
Chained In-Order/Out-of-Order DoubleCore Architecture. SBAC-PAD (2005)
Daniel A. Jiménez
Improved latency and accuracy for neural branch prediction. ACM Trans. Comput. Syst. 23 (2) (2005)
Ravi V. Batchu, Daniel A. Jiménez
Exploiting Procedure Level Locality to Reduce Instruction Cache Misses. Interaction between Compilers and Computer Architectures (2004)
Daniel A. Jiménez
Fast Path-Based Neural Branch Prediction. MICRO (2003)
Daniel A. Jiménez
Reconsidering Complex Branch Predictors. HPCA (2003)
Daniel A. Jiménez, Calvin Lin
Neural methods for dynamic branch prediction. ACM Trans. Comput. Syst. 20 (4) (2002)
Daniel A. Jiménez, Calvin Lin
Dynamic Branch Prediction with Perceptrons. HPCA (2001)
Daniel A. Jiménez, Heather L. Hanson, Calvin Lin
Boolean Formula-Based Branch Prediction for Future Technologies. IEEE PACT (2001)
Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin
The impact of delay on the design of branch predictors. MICRO (2000)