Gabriel H. Loh

ORCID

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 38

Top Venues

Publications

Alan Smith, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Samuel Naffziger, Mike Mantor, Nathan Kalyanasundharam, Vamsi Alla, Nicholas Malaya, Joseph L. Greathouse, Eric Chapman, Raja Swaminathan
Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. ISCA (2024)
Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, Johnathan Alsop, Paul T. Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William C. Brantley, Noel Chalmers, Shaoming Chen, Kevin Cheng, Michael L. Chu, David Cownie, Nicholas Curtis, Joris Del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish Kotra, Alan Lee, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliot Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Gregory Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, René van Oostrum, Eric Van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov
A Research Retrospective on AMD's Exascale Computing Journey. ISCA (2023)
Raja Swaminathan, Michael J. Schulte, Brett Wilkerson, Gabriel H. Loh, Alan Smith, Norman James
MI250X Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture. VLSI Technology and Circuits (2023)
Gabriel H. Loh, Raja Swaminathan
The Next Era for Chiplet Innovation. DATE (2023)
Gabriel H. Loh, Samuel Naffziger, Kevin Lepak
Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. DATE (2021)
Jagadish B. Kotra, Michael LeBeane, Mahmut T. Kandemir, Gabriel H. Loh
Increasing GPU Translation Reach by Leveraging Under-Utilized On-Chip Resources. MICRO (2021)
Salonik Resch, Anthony Gutierrez, Joon Suk Huh, Srikant Bharadwaj, Yasuko Eckert, Gabriel H. Loh, Mark Oskin, Swamit S. Tannu
Accelerating Variational Quantum Algorithms Using Circuit Concurrency. CoRR (2021)
Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, Sean White
Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product. ISCA (2021)
Mark Papermaster, Stephen Kosonocky, Gabriel H. Loh, Samuel Naffziger
A New Era of Tailored Computing. VLSI Circuits (2021)
Mohamed Assem Ibrahim, Onur Kayiran, Yasuko Eckert, Gabriel H. Loh, Adwait Jog
Analyzing and Leveraging Decoupled L1 Caches in GPUs. HPCA (2021)
Jieming Yin, Subhash Sethumurugan, Yasuko Eckert, Chintan Patel, Alan Smith, Eric Morton, Mark Oskin, Natalie D. Enright Jerger, Gabriel H. Loh
Experiences with ML-Driven Design: A NoC Case Study. HPCA (2020)
Mohamed Assem Ibrahim, Onur Kayiran, Yasuko Eckert, Gabriel H. Loh, Adwait Jog
Analyzing and Leveraging Shared L1 Caches in GPUs. PACT (2020)
Dylan C. Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie, Xueqi Li, Gabriel H. Loh
Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-Memory. DAC (2019)
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Mahmut T. Kandemir, Onur Mutlu
Holistic Management of the GPGPU Memory Hierarchy to Manage Warp-level Latency Tolerance. CoRR (2018)
Ján Veselý, Arkaprava Basu, Abhishek Bhattacharjee, Gabriel H. Loh, Mark Oskin, Steven K. Reinhardt
Generic System Calls for GPUs. ISCA (2018)
Jieming Yin, Zhifeng Lin, Onur Kayiran, Matthew Poremba, Muhammad Shoaib Bin Altaf, Natalie D. Enright Jerger, Gabriel H. Loh
Modular Routing Design for Chiplet-Based Systems. ISCA (2018)
Hyojong Kim, Ramyad Hadidi, Lifeng Nai, Hyesoon Kim, Nuwan Jayasena, Yasuko Eckert, Onur Kayiran, Gabriel H. Loh
CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems. ACM Trans. Archit. Code Optim. 15 (3) (2018)
Amin Farmahini Farahani, Sudhanva Gurumurthi, Gabriel H. Loh, Michael Ignatowski
Challenges of High-Capacity DRAM Stacks and Potential Directions. MCHPC@SC (2018)
Rachata Ausavarungnirun, Gabriel H. Loh, Lavanya Subramanian, Kevin K. Chang, Onur Mutlu
High-Performance and Energy-Effcient Memory Scheduler Design for Heterogeneous Systems. CoRR (2018)
Joseph L. Greathouse, Gabriel H. Loh
Machine learning for performance and power modeling of heterogeneous systems. ICCAD (2018)
Seunghee Shin, Guilherme Cox, Mark Oskin, Gabriel H. Loh, Yan Solihin, Abhishek Bhattacharjee, Arkaprava Basu
Scheduling Page Table Walks for Irregular GPU Applications. ISCA (2018)
Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen
MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories. HPCA (2017)
Hyojong Kim, Ramyad Hadidi, Lifeng Nai, Hyesoon Kim, Nuwan Jayasena, Yasuko Eckert, Onur Kayiran, Gabriel H. Loh
CODA: Enabling Co-location of Computation and Data for Near-Data Processing. CoRR (2017)
Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes. ISCA (2017)
Abhinav Agrawal, Gabriel H. Loh, James Tuck
Leveraging near data processing for high-performance checkpoint/restart. SC (2017)
Thiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan
Design and Analysis of an APU for Exascale Computing. HPCA (2017)
Amro Awad, Arkaprava Basu, Sergey Blagodurov, Yan Solihin, Gabriel H. Loh
Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries. PACT (2017)
Dylan C. Stow, Yuan Xie, Taniya Siddiqua, Gabriel H. Loh
Cost-effective design of scalable high-performance systems using active and passive interposers. ICCAD (2017)
Ján Veselý, Arkaprava Basu, Abhishek Bhattacharjee, Gabriel H. Loh, Mark Oskin, Steven K. Reinhardt
GPU System Calls. CoRR (2017)
Onur Kayiran, Adwait Jog, Ashutosh Pattnaik, Rachata Ausavarungnirun, Xulong Tang, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das
μC-States: Fine-grained GPU Datapath Power Management. PACT (2016)
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing. CoRR (2016)
Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures. MICRO (2016)
Ajaykumar Kannan, Natalie D. Enright Jerger, Gabriel H. Loh
Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors. IEEE Micro 36 (3) (2016)
Ján Veselý, Arkaprava Basu, Mark Oskin, Gabriel H. Loh, Abhishek Bhattacharjee
Observations and opportunities in architecting shared virtual memory for heterogeneous systems. ISPASS (2016)
Jieming Yin, Onur Kayiran, Matthew Poremba, Natalie D. Enright Jerger, Gabriel H. Loh
Efficient synthetic traffic models for large, complex SoCs. HPCA (2016)
Zhe Wang, Daniel A. Jiménez, Tao Zhang, Gabriel H. Loh, Yuan Xie
Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. SBAC-PAD (2016)
Kevin Kai-Wei Chang, Gabriel H. Loh, Mithuna Thottethodi, Yasuko Eckert, Mike O'Connor, Srilatha Manne, Lisa Hsu, Lavanya Subramanian, Onur Mutlu
Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism. CoRR (2016)
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate. Parallel Comput. 54 (2016)
Rachata Ausavarungnirun, Saugata Ghose, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Mahmut T. Kandemir, Onur Mutlu
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance. PACT (2015)
Chun-Yi Su, David Roberts, Edgar A. León, Kirk W. Cameron, Bronis R. de Supinski, Gabriel H. Loh, Dimitrios S. Nikolopoulos
HpMC: An Energy-aware Management System of Multi-level Memory Architectures. MEMSYS (2015)
Ajaykumar Kannan, Natalie D. Enright Jerger, Gabriel H. Loh
Enabling interposer-based disintegration of multi-core processors. MICRO (2015)
Michael J. Schulte, Mike Ignatowski, Gabriel H. Loh, Bradford M. Beckmann, William C. Brantley, Sudhanva Gurumurthi, Nuwan Jayasena, Indrani Paul, Steven K. Reinhardt, Gregory Rodgers
Achieving Exascale Capabilities through Heterogeneous Computing. IEEE Micro 35 (4) (2015)
Mitesh R. Meswani, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski, Gabriel H. Loh
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories. HPCA (2015)
Binh Pham, Ján Veselý, Gabriel H. Loh, Abhishek Bhattacharjee
Large pages and lightweight memory management in virtualized environments: can you have it both ways? MICRO (2015)
Gabriel H. Loh, Natalie D. Enright Jerger, Ajaykumar Kannan, Yasuko Eckert
Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems. MEMSYS (2015)
Mark Oskin, Gabriel H. Loh
A Software-Managed Approach to Die-Stacked DRAM. PACT (2015)
Daehyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). IEEE Trans. Computers 64 (1) (2015)
Onur Kayiran, Nachiappan Chidambaram Nachiappan, Adwait Jog, Rachata Ausavarungnirun, Mahmut T. Kandemir, Gabriel H. Loh, Onur Mutlu, Chita R. Das
Managing GPU Concurrency in Heterogeneous Architectures. MICRO (2014)
Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches. IEEE Micro 34 (3) (2014)
Rachata Ausavarungnirun, Chris Fallin, Xiangyao Yu, Kevin Kai-Wei Chang, Greg Nazario, Reetuparna Das, Gabriel H. Loh, Onur Mutlu
Design and Evaluation of Hierarchical Rings with Deflection Routing. SBAC-PAD (2014)
Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian
Managing DRAM Latency Divergence in Irregular GPGPU Applications. SC (2014)
Natalie D. Enright Jerger, Ajaykumar Kannan, Zimo Li, Gabriel H. Loh
NoC Architectures for Silicon Interposer Systems: Why Pay for more Wires when you Can Get them (from your interposer) for Free? MICRO (2014)
Mitesh R. Meswani, Gabriel H. Loh, Sergey Blagodurov, David Roberts, John Slice, Mike Ignatowski
Toward efficient programmer-managed two-level memory hierarchies in exascale computers. Co-HPC@SC (2014)
Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez, Gabriel H. Loh
Last-level cache deduplication. ICS (2014)
Binh Pham, Abhishek Bhattacharjee, Yasuko Eckert, Gabriel H. Loh
Increasing TLB reach by exploiting clustering in page translations. HPCA (2014)
Djordje Jevdjic, Gabriel H. Loh, Cansu Kaynak, Babak Falsafi
Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache. MICRO (2014)
Hyeran Jeon, Gabriel H. Loh, Murali Annavaram
Efficient RAS support for die-stacked DRAM. ITC (2014)
Babak Falsafi, Gabriel H. Loh
Top Picks from the 2012 Computer Architecture Conferences. IEEE Micro 33 (3) (2013)
Yuan Xie, Gabriel H. Loh
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (4) (2013)
Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
Resilient die-stacked DRAM caches. ISCA (2013)
Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie
Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Gabriel H. Loh, Mark D. Hill
Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap. IEEE Micro 32 (3) (2012)
Moinuddin K. Qureshi, Gabriel H. Loh
Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design. MICRO (2012)
Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie
Energy-efficient GPU design with reconfigurable in-package graphics memory. ISLPED (2012)
Kiyoung Choi, John Kim, Gabriel H. Loh
Guest Editorial New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (2) (2012)
Gabriel H. Loh
Computer architecture for die stacking. VLSI-DAT (2012)
Rachata Ausavarungnirun, Kevin Kai-Wei Chang, Lavanya Subramanian, Gabriel H. Loh, Onur Mutlu
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems. ISCA (2012)
John Kim, Kiyoung Choi, Gabriel H. Loh
Exploiting New Interconnect Technologies in On-Chip Communication. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (2) (2012)
Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi
A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. MICRO (2012)
Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC (2012)
Gabriel H. Loh
A register-file approach for row buffer caches in die-stacked DRAMs. MICRO (2011)
Yuejian Xie, Gabriel H. Loh
Thread-aware dynamic shared cache compression in multi-core processors. ICCD (2011)
Andrew W. Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger
Preventing PCM banks from seizing too much power. MICRO (2011)
Gabriel H. Loh, Mark D. Hill
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. MICRO (2011)
Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger
Use ECP, not ECC, for hard failures in resistive memories. ISCA (2010)
Gabriel H. Loh, Yuan Xie
3D Stacked Microprocessor: Are We There Yet? IEEE Micro 30 (3) (2010)
Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim
Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC (2010)
Yuejian Xie, Gabriel H. Loh
Scalable Shared-Cache Management by Containing Thrashing Workloads. HiPEAC (2010)
Serkan Ozdemir, Yan Pan, Abhishek Das, Gokhan Memik, Gabriel H. Loh, Alok N. Choudhary
Quantifying and coping with parametric variations in 3D-stacked microarchitectures. DAC (2010)
Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim
Thermal optimization in multi-granularity multi-core floorplanning. ASP-DAC (2009)
Samantika Subramaniam, Gabriel H. Loh
Design and optimization of the store vectors memory dependence predictor. ACM Trans. Archit. Code Optim. 6 (4) (2009)
Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh
Criticality-based optimizations for efficient load processing. HPCA (2009)
Gabriel H. Loh
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy. MICRO (2009)
Kiran Puttaswamy, Gabriel H. Loh
3D-Integrated SRAM Components for High-Performance Microprocessors. IEEE Trans. Computers 58 (10) (2009)
Yuejian Xie, Gabriel H. Loh
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. ISCA (2009)
Gabriel H. Loh, Samantika Subramaniam, Yuejian Xie
Zesto: A cycle-level simulator for highly detailed microarchitecture exploration. ISPASS (2009)
Gabriel H. Loh, Daniel A. Jiménez
Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors. Int. J. Parallel Program. 36 (2) (2008)
Samantika Subramaniam, Milos Prvulovic, Gabriel H. Loh
PEEP: Exploiting predictability of memory dependences in SMT processors. HPCA (2008)
Maurício Breternitz Jr., Gabriel H. Loh, Bryan Black, Jeff Rupley, Peter G. Sassone, Wesley Attrot, Youfeng Wu
A Segmented Bloom Filter Algorithm for Efficient Predictors. SBAC-PAD (2008)
Gabriel H. Loh
A modular 3d processor for flexible product design and technology migration. Conf. Computing Frontiers (2008)
Gabriel H. Loh
3D-Stacked Memory Architectures for Multi-core Processors. ISCA (2008)
Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, Gabriel H. Loh, Bryan Black
Matrix scheduler reloaded. ISCA (2007)
Kiran Puttaswamy, Gabriel H. Loh
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors. DAC (2007)
Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, Gabriel H. Loh
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (1) (2007)
Peter G. Sassone, D. Scott Wills, Gabriel H. Loh
Static strands: Safely exposing dependence chains for increasing embedded power efficiency. ACM Trans. Embed. Comput. Syst. 6 (4) (2007)
Kiran Puttaswamy, Gabriel H. Loh
Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. HPCA (2007)
Gabriel H. Loh, Yuan Xie, Bryan Black
Processor Design in 3D Die-Stacking Technologies. IEEE Micro 27 (3) (2007)
Kiran Puttaswamy, Gabriel H. Loh
Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology. ISVLSI (2006)
Kiran Puttaswamy, Gabriel H. Loh
Thermal analysis of a 3D die-stacked high-performance microprocessor. ACM Great Lakes Symposium on VLSI (2006)
Daniel A. Jiménez, Gabriel H. Loh
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. SBAC-PAD (2006)

Gabriel H. Loh.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Gabriel H. Loh