Samuel Naffziger

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 20

Top Topics

Tier Architecture

Singular Points

Power Management

Top Venues

IEEE J. Solid State Circuits

Publications

Alan Smith, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Samuel Naffziger, Mike Mantor, Nathan Kalyanasundharam, Vamsi Alla, Nicholas Malaya, Joseph L. Greathouse, Eric Chapman, Raja Swaminathan
Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. ISCA (2024)
John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. ISSCC (2022)
Gabriel H. Loh, Samuel Naffziger, Kevin Lepak
Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. DATE (2021)
Samuel Naffziger, Noah Beck, Thomas Burd, Kevin Lepak, Gabriel H. Loh, Mahesh Subramony, Sean White
Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product. ISCA (2021)
Mark Papermaster, Stephen Kosonocky, Gabriel H. Loh, Samuel Naffziger
A New Era of Tailored Computing. VLSI Circuits (2021)
Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag
SE1: What Technologies Will Shape the Future of Computing? ISSCC (2021)
Samuel Naffziger, Kevin Lepak, Milam Paraschou, Mahesh Subramony
2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. ISSCC (2020)
Sal Dasgupta, Teja Singh, Ashish Jain, Samuel Naffziger, Deepesh John, Chetan Bisht, Pradeep Jayaraman
8.4 Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs. ISSCC (2020)
Thomas Burd, Noah Beck, Sean White, Milam Paraschou, Nathan Kalyanasundharam, Gregg Donley, Alan Smith, Larry Hewitt, Samuel Naffziger
"Zeppelin": An SoC for Multichip Architectures. IEEE J. Solid State Circuits 54 (1) (2019)
Teja Singh, Alex Schaefer, Sundar Rangarajan, Deepesh John, Carson Henrion, Russell Schreiber, Miguel Rodriguez, Stephen Kosonocky, Samuel Naffziger, Amy Novak
Zen: An Energy-Efficient High-Performance × 86 Core. IEEE J. Solid State Circuits 53 (1) (2018)
Noah Beck, Sean White, Milam Paraschou, Samuel Naffziger
'Zeppelin': An SoC for multichip architectures. ISSCC (2018)
Sriram Sundaram, Aaron Grenat, Samuel Naffziger, Tom Burd, Stephen Kosonocky, Steven Liepe, Ravinder Rachala, Miguel Rodriguez, Michael Austin, Sriram Sambamurthy
Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. IEEE J. Solid State Circuits 52 (1) (2017)
Aaron Grenat, Sriram Sundaram, Stephen Kosonocky, Ravinder Rachala, Sriram Sambamurthy, Steven Liepe, Miguel Rodriguez, Tom Burd, Adam Clark, Michael Austin, Samuel Naffziger
4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. ISSCC (2016)
Guhan Krishnan, Dan Bouvier, Samuel Naffziger
Energy-Efficient Graphics and Multimedia in 28-nm Carrizo Accelerated Processing Unit. IEEE Micro 36 (2) (2016)
Sriram Sundaram, Warren He, Sriram Sambamurthy, Aaron Grenat, Steven Liepe, Samuel Naffziger
Unified Power Frequency Model Framework. ISLPED (2016)
Sriram Sundaram, Sriram Sambamurthy, Michael Austin, Aaron Grenat, Michael Golden, Stephen Kosonocky, Samuel Naffziger
Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU. VLSI Design (2016)
Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox
Carrizo: A High Performance, Energy Efficient 28 nm APU. IEEE J. Solid State Circuits 51 (1) (2016)
Samuel Naffziger, Guri Sohi
Hot Chips 26 [Guest editors' introduction]. IEEE Micro 35 (2) (2015)
Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White
4.8 A 28nm x86 APU optimized for power and area efficiency. ISSCC (2015)
Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White
Steamroller Module and Adaptive Clocking System in 28 nm CMOS. IEEE J. Solid State Circuits 50 (1) (2015)
Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. ISSCC (2014)
Samuel Naffziger, Guri Sohi
Welcome program chairs. Hot Chips Symposium (2014)
Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits 48 (1) (2013)
Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. IEEE J. Solid State Circuits 47 (1) (2012)
Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC (2012)
Steve J. Dillen, Donald A. Priore, Aaron Horiuchi, Samuel Naffziger
Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules. CICC (2012)
Timothy Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. ISSCC (2011)
Hanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon
at 81% efficiency. ISSCC (2010)
Rich McGowen, Christopher Poirier, Chris Bostak, Jim Ignowski, Mark Millican, Warren H. Parks, Samuel Naffziger
Power and temperature control on a 90-nm Itanium family processor. IEEE J. Solid State Circuits 41 (1) (2006)
Tim Fischer, Jayen Desai, Bruce Andrew Doyle, Samuel Naffziger, Ben Patella
A 90-nm variable frequency clock system for a power-managed itanium architecture processor. IEEE J. Solid State Circuits 41 (1) (2006)
Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz
The implementation of a 2-core, multi-threaded itanium family processor. IEEE J. Solid State Circuits 41 (1) (2006)