Harry R. Fair III

Publication Activity (10 Years)

Years Active: 1995-2023
Publications (10 Years): 4

Top Topics

Cmos Technology

High Reliability

Data Aggregation

Top Venues

IEEE J. Solid State Circuits

Publications

Benjamin Munger, Kathy Wilcox, Jeshuah Sniderman, Chuck Tung, Brett Johnson, Russell Schreiber, Carson Henrion, Kevin Gillespie, Tom Burd, Harry R. Fair III, Dave Johnson, Jonathan White, Scott McLelland, Steven Bakke, Javin Olson, Ryan McCracken, Matthew Pickett, Aaron Horiuchi, Hien Nguyen, Tim Jackson
"Zen 4": The AMD 5nm 5.7GHz x86-64 Microprocessor Core. ISSCC (2023)
Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox
Carrizo: A High Performance, Energy Efficient 28 nm APU. IEEE J. Solid State Circuits 51 (1) (2016)
Kathryn Wilcox, David Akeson, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White
4.8 A 28nm x86 APU optimized for power and area efficiency. ISSCC (2015)
Kathryn Wilcox, Robert Cole, Harry R. Fair III, Kevin Gillespie, Aaron Grenat, Carson Henrion, Ravi Jotwani, Stephen Kosonocky, Benjamin Munger, Samuel Naffziger, Robert S. Orefice, Sanjay Pant, Donald A. Priore, Ravinder Rachala, Jonathan White
Steamroller Module and Adaptive Clocking System in 28 nm CMOS. IEEE J. Solid State Circuits 50 (1) (2015)
Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. ISSCC (2014)
William J. Bowhill, Shane L. Bell, Bradley J. Benschneider, Andrew J. Black, Sharon M. Britton, Ruben W. Castelino, Dale R. Donchin, John H. Edmondson, Harry R. Fair III, Paul E. Gronowski, Anil K. Jain, Patricia L. Kroesen, Marc E. Lamere, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Ronald P. Preston, Sribalan Santhanam, Timothy A. Shedd, Michael J. Smith, Stephen C. Thierauf
Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU Digit. Tech. J. 7 (1) (1995)