Ken Takeuchi

ORCID

Publication Activity (10 Years)

Years Active: 1983-2024
Publications (10 Years): 75

Top Venues

ISCAS

IEICE Trans. Electron.

IEEE J. Solid State Circuits

A-SSCC

Publications

Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing. IEEE Trans. Very Large Scale Integr. Syst. 32 (3) (2024)
Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi
Embedded Transformer Hetero-CiM: SRAM CiM for 4b Read/Write-MAC Self-attention and MLC ReRAM CiM for 6b Read-MAC Linear&FC Layers. IMW (2024)
Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect Tolerance. IMW (2023)
Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi
Write Variation & Reliability Error Compensation by Layer-Wise Tunable Retraining of Edge FeFET LM-GA CiM. IEICE Trans. Electron. 106 (7) (2023)
Ken Takeuchi
Neuromorphic Computation-in-Memory System (Invited). IRPS (2023)
Ken Takeuchi
Analog Computation-in-Memory (CiM) for AI Applications. ICICDT (2023)
Ken Takeuchi
Foreword. A-SSCC (2023)
Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
ReRAM CiM Fluctuation Pattern Classification by CNN Trained on Artificially Created Dataset. IRPS (2023)
Ayumu Yamada, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
LIORAT: NN Layer I/O Range Training for Area/Energy-Efficient Low-Bit A/D Conversion System Design in Error-Tolerant Computation-in-Memory. ICCAD (2023)
Chihiro Matsui, Ken Takeuchi
Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant Workloads. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Yuya Ichikawa, Akira Goda, Chihiro Matsui, Ken Takeuchi
Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM. IMW (2022)
Chihiro Matsui, Eitaro Kobayashi, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
Versatile FeFET Voltage-sensing Analog CiM for Fast & Small-area Hyperdimensional Computing. ISCAS (2022)
Shinsei Yoshikiyo, Naoko Misawa, Chihiro Matsui, Ken Takeuchi
Edge Computation-in-Memory for In-situ Class-incremental Learning with Knowledge Distillation. ISCAS (2022)
Naoko Misawa, Kenta Taoka, Chihiro Matsui, Ken Takeuchi
Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing. ISCAS (2022)
Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi
Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation. IMW (2022)
Kenta Taoka, Naoko Misawa, Shunsuke Koshino, Chihiro Matsui, Ken Takeuchi
Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory. IMW (2021)
Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing. VLSI Circuits (2021)
Mamoru Fukuchi, Shun Suzuki, Kyosuke Maeda, Chihiro Matsui, Ken Takeuchi
BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads. ISCAS (2021)
Daiki Kojima, Ken Takeuchi
Error Suppression of Last-Programmed Word-Line for Real Usage of 3D-NAND Flash Memory. ISCAS (2021)
Hugh Mair, Shinichiro Shiratake, Eric Karl, Thomas Burd, Jonathan Chang, Debbie Marr, Samuel Naffziger, Henk Corporaal, Ken Takeuchi, Naresh R. Shanbhag
SE1: What Technologies Will Shape the Future of Computing? ISSCC (2021)
Mamoru Fukuchi, Chihiro Matsui, Ken Takeuchi
System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs. IEICE Trans. Electron. (4) (2020)
Ken Takeuchi, Brian P. Ginsburg
Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 55 (4) (2020)
Yoshiki Kakuta, Reika Kinoshita, Hiroshi Kinoshita, Chihiro Matsui, Ken Takeuchi
Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers. VLSI-DAT (2020)
Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita, Ken Takeuchi
Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs). IEICE Trans. Electron. (4) (2020)
Reika Kinoshita, Chihiro Matsui, Atsuya Suzuki, Shouhei Fukuyama, Ken Takeuchi
Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance. ASP-DAC (2020)
Shun Suzuki, Hiroki Aihara, Ken Takeuchi
Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing. IEEE J. Solid State Circuits 55 (10) (2020)
Chihiro Matsui, Ken Takeuchi
Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories. ISCAS (2019)
Ken Chang, Ken Takeuchi
Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 54 (4) (2019)
Koki Kamimura, Susumu Nohmi, Kenta Suzuki, Ken Takeuchi
Parallel Product-Sum Operation Neuromorphic Systems with 4-bit Ferroelectric FET Synapses. ESSDERC (2019)
Chihiro Matsui, Ken Takeuchi
Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories. ASP-DAC (2019)
Kyoji Mizoguchi, Kyosuke Maeda, Ken Takeuchi
Automatic Data Repair Overwrite Pulse for 3D-TLC NAND Flash Memories with 38x Data-Retention Lifetime Extension. IRPS (2019)
Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories. IEEE J. Solid State Circuits 54 (3) (2019)
Shun Suzuki, Kyoji Mizoguchi, Hikaru Watanabe, Toshiki Nakamura, Yoshiaki Deguchi, Keita Mizushina, Ken Takeuchi
Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing. A-SSCC (2019)
Toshiro Hiramoto, K. Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, T. Sarava, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, H. Ohashi, K. Itou, T. Takakura, M. Fukui, S. Suzuki, Ken Takeuchi, Masanori Tsukuda, Y. Numasawa
Switching of 3300V Scaled IGBT by 5V Gate Drive. ASICON (2019)
Chihiro Matsui, Ken Takeuchi
Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. 27 (8) (2019)
Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa, Ken Takeuchi
3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition. IEEE J. Solid State Circuits 54 (6) (2019)
Shouhei Fukuyama, Atsuna Hayakawa, Ryutaro Yasuhara, Shinpei Matsuda, Hiroshi Kinoshita, Ken Takeuchi
Comprehensive Analysis of Data-Retention and Endurance Trade-Off of 40nm TaOx-based ReRAM. IRPS (2019)
Chihiro Matsui, Ken Takeuchi
Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. Integr. 69 (2019)
Kota Tsurumi, Kenta Suzuki, Ken Takeuchi
A 6.8 TOPS/W Energy Efficiency, 1.5µW Power Consumption, Pulse Width Modulation Neuromorphic Circuits for Near-Data Computing with SSD. A-SSCC (2018)
Yoshiaki Deguchi, Shun Suzuki, Ken Takeuchi
Modulation for 2-D and 3-D-TLC NAND Flash Memories. IEEE J. Solid State Circuits 53 (10) (2018)
Mamoru Fukuchi, Yukiya Sakaki, Chihiro Matsui, Ken Takeuchi
20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD. ISCAS (2018)
Atsuya Suzuki, Chihiro Matsui, Ken Takeuchi
Periodic Data Eviction Algorithm of SCM/NAND Flash Hybrid SSD with SCM Retention Time Constraint Capabilities at Extremely High Temperature. NVMTS (2018)
Hirofumi Takishita, Yutaka Adachi, Chihiro Matsui, Ken Takeuchi
Analysis of SCM-Based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size. IEICE Trans. Electron. (4) (2018)
Kazuki Maeda, Shinpei Matsuda, Ken Takeuchi, Ryutaro Yasuhara
Observation and Analysis of Bit-by-Bit Cell Current Variation During Data-Retention of TaOx-based ReRAM. ESSDERC (2018)
Keita Mizushina, Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition. ISCAS (2018)
Yusuke Yamaga, Chihiro Matsui, Yukiya Sakaki, Ken Takeuchi
Reliability Analysis of Scaled NAND Flash Memory Based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test. IEICE Trans. Electron. (4) (2018)
Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi
Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs. IRPS (2018)
Chihiro Matsui, Ken Takeuchi
3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage. ISCAS (2018)
Atsuna Hayakawa, Toshiki Nakamura, Yoshiaki Deguchi, Kazuki Maeda, Ken Takeuchi
Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network. ISCAS (2018)
Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories. CICC (2018)
Yutaka Adachi, Chihiro Matsui, Ken Takeuchi
Double asymmetric-latency storage class memories (SCMs) for fast-write SCM, fast-read SCM & NAND flash hybrid SSDs. VLSI-DAT (2018)
Shouhei Fukuyama, Shinpei Matsuda, Ryutaro Yasuhara, Ken Takeuchi
Improvement of Endurance and Data-retention in 40nm TaOX-based ReRAM by Finalize Verify. NVMTS (2018)
Shouhei Fukuyama, Kazuki Maeda, Shinpei Matsuda, Ken Takeuchi, Ryutaro Yasuhara
Suppression of endurance-stressed data-retention failures of 40nm TaOx-based ReRAM. IRPS (2018)
Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Ken Takeuchi
Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x. ESSDERC (2018)
Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, H. Ohashi, Hiroshi Iwai
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. VLSI Circuits (2018)
Reika Kinoshita, Chihiro Matsui, Shinpei Matsuda, Yutaka Adachi, Ken Takeuchi
Maximizing Peformance/cost Figure of Merit of Storage-type SCM based SSD by Adding Small Capacity of Memory-type SCM. NVMTS (2018)
Kota Tsurumi, Masahiro Tanaka, Ken Takeuchi
0.6 V operation, 16 % faster set/reset ReRAM boost converter with adaptive buffer voltage for ReRAM and NAND flash hybrid solid-state drives. ISQED (2017)
Hirokazu Nosato, Hidenori Sakanashi, Eiichi Takahashi, Masahiro Murakawa, Hiroshi Aoki, Ken Takeuchi, Yasuo Suzuki
Image Retrieval Method for Multiscale Objects from Optical Colonoscopy Images. Int. J. Biomed. Imaging 2017 (2017)
Chihiro Matsui, Asuka Arakawa, Chao Sun, Ken Takeuchi
Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD. IEEE Trans. Very Large Scale Integr. Syst. 25 (2) (2017)
Takashi Inose, Seiichi Aritome, Ryutaro Yasuhara, Satoshi Mishima, Ken Takeuchi
Study of error repeatability and recovery in 40nm TaOx ReRAM. ESSDERC (2017)
Chihiro Matsui, Chao Sun, Ken Takeuchi
Design of Hybrid SSDs With Storage Class Memory and NAND Flash Memory. Proc. IEEE 105 (9) (2017)
Yoshiaki Deguchi, Ken Takeuchi
Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data. A-SSCC (2017)
Tomoaki Yamada, Chihiro Matsui, Ken Takeuchi
Workload-Based Co-Design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs. IEICE Trans. Electron. (4) (2017)
Chihiro Matsui, Ken Takeuchi
22% Higher performance, 2x SCM write endurance heterogeneous storage with dual storage class memory and NAND flash. ESSDERC (2017)
Yoshiaki Deguchi, Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi
12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition. CICC (2017)
Hikaru Watanabe, Yoshiaki Deguchi, Ken Takeuchi
MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage. A-SSCC (2017)
Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes, Ken Takeuchi
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. IEEE J. Solid State Circuits 51 (8) (2016)
Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita, Ken Takeuchi
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Hirofumi Takishita, Shuhei Tanakamaru, Sheyang Ning, Ken Takeuchi
Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths. IEICE Trans. Electron. (4) (2016)
Atsuro Kobayashi, Tsukasa Tokutomi, Ken Takeuchi
Versatile TLC NAND flash memory control to reduce read disturb errors by 85% and extend read cycles by 6.7-times of Read-Hot and Cold data for cloud data centers. VLSI Circuits (2016)
Masahiro Tanaka, Kota Tsurumi, Tomoya Ishii, Ken Takeuchi
Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process. ESSCIRC (2016)
Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories. IEEE J. Solid State Circuits 51 (4) (2016)
Tomoya Ishii, Sheyang Ning, Masahiro Tanaka, Kota Tsurumi, Ken Takeuchi
Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications. IEEE J. Solid State Circuits 51 (10) (2016)
Chao Sun, Ayumi Soga, Chihiro Matsui, Asuka Arakawa, Ken Takeuchi
LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Chao Sun, Shun Okamoto, Shogo Hachiya, Tomoaki Yamada, Ken Takeuchi
Design guidelines of storage class memory/flash hybrid solid-state drive considering system architecture, algorithm and workload characteristic. IEEE Trans. Consumer Electron. 62 (3) (2016)
Shuhei Tanakamaru, Hiroki Yamazawa, Ken Takeuchi
Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten. VLSIC (2015)
Chao Sun, Asuka Arakawa, Ken Takeuchi
SEA-SSD: A Storage Engine Assisted SSD With Application-Coupled Simulation Platform. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2015)
Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Tomoya Ishii, Shogo Hachiya, Sheyang Ning, Masahiro Tanaka, Ken Takeuchi
0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications. A-SSCC (2015)
Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi
Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory. VLSIC (2015)
Senju Yamazaki, Shuhei Tanakamaru, Sakuya Suzuki, Tomoko Ogura Iwasaki, Shogo Hachiya, Ken Takeuchi
Reliability enhancement of 1Xnm TLC for cold flash and millennium memories. VLSIC (2015)
Tsukasa Tokutomi, Masafumi Doi, Shogo Hachiya, Atsuro Kobayashi, Shuhei Tanakamaru, Ken Takeuchi
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. ISSCC (2015)
Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi
A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories. IEICE Trans. Electron. (1) (2015)
Shogo Hachiya, Takahiro Onagi, Sheyang Ning, Ken Takeuchi
Comprehensive comparison of 3D-TSV integrated solid-state drives (SSDs) with storage class memory and NAND flash memory. 3DIC (2015)
Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi
Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs). IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Chao Sun, Ayumi Soga, Takahiro Onagi, Koh Johguchi, Ken Takeuchi
A workload-aware-design of 3D-NAND flash memory for enterprise SSDs. ISQED (2014)
Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi
19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers. ISSCC (2014)
Ken Takeuchi
Hybrid solid-state storage system with storage class memory and NAND flash memory for big-data application. ISCAS (2014)
Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi
NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2014)
Chao Sun, Kousuke Miyaji, Koh Johguchi, Ken Takeuchi
A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2014)
Chao Sun, Tomoko Ogura Iwasaki, Takahiro Onagi, Koh Johguchi, Ken Takeuchi
Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2014)
Koh Johguchi, Kasuaki Yoshioka, Ken Takeuchi
NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance. IEICE Trans. Electron. (4) (2014)
Koh Johguchi, Toru Egami, Kousuke Miyaji, Ken Takeuchi
A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories. IEICE Trans. Electron. (4) (2014)
Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi
Application-aware solid-state drives (SSDs) with adaptive coding. VLSIC (2014)
Chao Sun, Hiroki Fujii, Kousuke Miyaji, Koh Johguchi, Kazuhide Higuchi, Ken Takeuchi
Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression. ASP-DAC (2013)
Ken Takeuchi
Scaling challenges of NAND flash memory and hybrid memory system with storage class memory & NAND flash memory. CICC (2013)
Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi
Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs). IEEE J. Solid State Circuits 48 (11) (2013)
Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi
Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications. ISSCC (2013)
Kousuke Miyaji, Toshikazu Suzuki, Shinji Miyano, Ken Takeuchi
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy. IEEE J. Solid State Circuits 48 (9) (2013)
Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. ASP-DAC (2013)

Ken Takeuchi.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Ken Takeuchi