Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory.
Sheyang NingTomoko Ogura IwasakiShuhei TanakamaruDarlene VivianiHenry HuangMonte ManningThomas RueckesKen TakeuchiPublished in: IEEE J. Solid State Circuits (2016)
Keyphrases
- bit error rate
- bit errors
- soft decision
- fading channels
- computer simulation
- decoding complexity
- signal to noise ratio
- decoding algorithm
- multipath
- error correction
- random access
- channel coding
- analytical model
- mc cdma
- decision feedback
- turbo codes
- wireless channels
- transmission scheme
- channel errors
- main memory
- ultra wideband
- response time
- memory access
- data streams