Shuhei Tanakamaru

Publication Activity (10 Years)

Years Active: 2010-2016
Publications (10 Years): 9

Top Topics

Error Correction

Highly Reliable

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEICE Trans. Electron.

Publications

Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes, Ken Takeuchi
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. IEEE J. Solid State Circuits 51 (8) (2016)
Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita, Ken Takeuchi
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Hirofumi Takishita, Shuhei Tanakamaru, Sheyang Ning, Ken Takeuchi
Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths. IEICE Trans. Electron. (4) (2016)
Shuhei Tanakamaru, Hiroki Yamazawa, Ken Takeuchi
Privacy-protection solid-state storage (PP-SSS) system: Automatic lifetime management of internet-data's right to be forgotten. VLSIC (2015)
Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Senju Yamazaki, Shuhei Tanakamaru, Sakuya Suzuki, Tomoko Ogura Iwasaki, Shogo Hachiya, Ken Takeuchi
Reliability enhancement of 1Xnm TLC for cold flash and millennium memories. VLSIC (2015)
Tsukasa Tokutomi, Masafumi Doi, Shogo Hachiya, Atsuro Kobayashi, Shuhei Tanakamaru, Ken Takeuchi
7.7 Enterprise-grade 6x fast read and 5x highly reliable SSD with TLC NAND-flash memory for big-data storage. ISSCC (2015)
Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi
A Design Strategy of Error-Prediction Low-Density Parity-Check (EP-LDPC) Error-Correcting Code (ECC) and Error-Recovery Schemes for Scaled NAND Flash Memories. IEICE Trans. Electron. (1) (2015)
Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi
Highly Reliable Coding Methods for Emerging Applications: Archive and Enterprise Solid-State Drives (SSDs). IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2015)
Shuhei Tanakamaru, Hiroki Yamazawa, Tsukasa Tokutomi, Sheyang Ning, Ken Takeuchi
19.6 Hybrid storage of ReRAM/TLC NAND Flash with RAID-5/6 for cloud data centers. ISSCC (2014)
Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi
NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2014)
Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi
Application-aware solid-state drives (SSDs) with adaptive coding. VLSIC (2014)
Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi
Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs). IEEE J. Solid State Circuits 48 (11) (2013)
Shuhei Tanakamaru, Masafumi Doi, Ken Takeuchi
Unified solid-state-storage architecture with NAND flash memory and ReRAM that tolerates 32× higher BER for big-data applications. ISSCC (2013)
Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi
Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme. ASP-DAC (2013)
Ken Takeuchi, Teruyoshi Hatanaka, Shuhei Tanakamaru
Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs). IEICE Electron. Express 9 (8) (2012)
Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi
Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor. IEICE Trans. Electron. (4) (2012)
Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi
Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme. ISSCC (2012)
Shuhei Tanakamaru, Chinglin Hung, Ken Takeuchi
Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming. IEEE J. Solid State Circuits 47 (1) (2012)
Shuhei Tanakamaru, Chinglin Hung, Atsushi Esumi, Mitsuyoshi Ito, Kai Li, Ken Takeuchi
95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. ISSCC (2011)
Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano, Ken Takeuchi
Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection. IEEE J. Solid State Circuits 46 (9) (2011)
Shuhei Tanakamaru, Ken Takeuchi
Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems. IEEE J. Solid State Circuits 46 (10) (2011)
Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru, Shinji Miyano, Ken Takeuchi
Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. CICC (2010)