Yoshiaki Deguchi

Publication Activity (10 Years)

Years Active: 2017-2019
Publications (10 Years): 12

Top Topics

Image Recognition

Error Reduction

Top Venues

IEEE J. Solid State Circuits

Publications

Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories. IEEE J. Solid State Circuits 54 (3) (2019)
Shun Suzuki, Kyoji Mizoguchi, Hikaru Watanabe, Toshiki Nakamura, Yoshiaki Deguchi, Keita Mizushina, Ken Takeuchi
Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing. A-SSCC (2019)
Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa, Ken Takeuchi
3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition. IEEE J. Solid State Circuits 54 (6) (2019)
Yoshiaki Deguchi, Shun Suzuki, Ken Takeuchi
Modulation for 2-D and 3-D-TLC NAND Flash Memories. IEEE J. Solid State Circuits 53 (10) (2018)
Keita Mizushina, Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition. ISCAS (2018)
Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi, Ken Takeuchi
Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs. IRPS (2018)
Atsuna Hayakawa, Toshiki Nakamura, Yoshiaki Deguchi, Kazuki Maeda, Ken Takeuchi
Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network. ISCAS (2018)
Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi
9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories. CICC (2018)
Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Ken Takeuchi
Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x. ESSDERC (2018)
Yoshiaki Deguchi, Ken Takeuchi
Word-line batch Vth modulation of TLC NAND flash memories for both write-hot and cold data. A-SSCC (2017)
Yoshiaki Deguchi, Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi
12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition. CICC (2017)
Hikaru Watanabe, Yoshiaki Deguchi, Ken Takeuchi
MLC/3LC NAND flash SSD cache with asymmetric error reduction huffman coding for tiered hierarchical storage. A-SSCC (2017)