Toshiro Hiramoto

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 14

Top Topics

Cmos Image Sensor

Wide Dynamic Range

Silicon Dioxide

Top Venues

VLSI Technology and Circuits

Publications

Masaharu Kobayashi, Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka
Performance and Reliability of Nanosheet Oxide Semiconductor FETs with ALD-Grown InGaO for 3D Integration (Invited). IRPS (2024)
Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi
A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices. VLSI Technology and Circuits (2023)
Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
3-Layer stacked pixel-parallel CMOS image sensors using hybrid bonding of SOI wafers. Imaging Sensors and Systems (2022)
Toshiro Hiramoto, Takuya Saraya
Recent Progress of Double/Dual-Gate Silicon IGBT Technologies. ASICON (2021)
Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto
An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. AICAS (2020)
Masahide Goto, Joeri De Vos, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi, Yuki Honda, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers. 3DIC (2019)
Masaharu Kobayashi, Chengji Jin, Toshiro Hiramoto
Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric Model. ASICON (2019)
Toshiro Hiramoto, K. Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, K. Furukawa, M. Watanabe, N. Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, T. Sarava, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, H. Ohashi, K. Itou, T. Takakura, M. Fukui, S. Suzuki, Ken Takeuchi, Masanori Tsukuda, Y. Numasawa
Switching of 3300V Scaled IGBT by 5V Gate Drive. ASICON (2019)
Fei Mo, Yusaku Tagawa, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi
Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method. NVMTS (2019)
Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration. ISCAS (2018)
Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, H. Ohashi, Hiroshi Iwai
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. VLSI Circuits (2018)
Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately. ESSDERC (2018)
Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi
Parallel nonvolatile programming of power-up states of SRAM cells. ASICON (2017)
Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, H. Ohashi, Hiroshi Iwai
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). ASICON (2017)
Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto
Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers. 3DIC (2015)
Kosmas Galatsis, Paolo Gargini, Toshiro Hiramoto, Dirk Beernaert, Roger DeKeersmaecker, Joachim Pelka, Lothar Pfitzner
Nanoelectronics Research Gaps and Recommendations: A Report from the International Planning Working Group on Nanoelectronics (IPWGN) [Commentary]. IEEE Technol. Soc. Mag. 34 (2) (2015)
Toshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano
Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress. IEICE Trans. Electron. (6) (2013)
Tomoko Mizutani, Anil Kumar, Toshiro Hiramoto
Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs. IEICE Trans. Electron. (5) (2013)
Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto
NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM. IEICE Trans. Electron. (5) (2013)
Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya
Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs. CICC (2011)
Toshiro Hiramoto
Ultra-low-voltage operation: device perspective. ISLPED (2011)
George Bourianoff, Michel Brillouët, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida
Nanoelectronics Research for Beyond CMOS Information Processing. Proc. IEEE 98 (12) (2010)
Michel Brillouët, George Bourianoff, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida
Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps. Proc. IEEE 98 (12) (2010)
Toshiro Hiramoto, Toshiharu Nagumo, Tetsu Ohtou, Kouki Yokoyama
Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations. IEICE Trans. Electron. (4) (2007)
Toshiro Hiramoto, Masumi Saitoh, Gen Tsutsui
Emerging nanoscale silicon devices taking advantage of nanostructure physics. IBM J. Res. Dev. 50 (4-5) (2006)
Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai
Variable threshold CMOS (VTCMOS) in series connected circuits. ISLPED (2001)
Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. ISLPED (2001)
Takashi Inukai, Makoto Takamiya, Kouichi Nose, Hiroshi Kawaguchi, Toshiro Hiramoto, Takayasu Sakurai
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration. CICC (2000)
Nobuo Tamba, Akio Anzai, Kazuhiro Akimoto, Masayuki Ohayashi, Toshiro Hiramoto, Tadanori Kokubu, Sohei Ohmori, Tetsuya Muraya, Atsuyuki Kishimoto, Sousuke Tsuji, Hideki Hayashi, Nadateru Handa, Toshio Igarashi, Hiroaki Nambu, Makoto Yoshida, Tsuyoshi Fujiwara, Kunihiko Watanabe, Akihisa Uchida, Masanori Odaka, Kunihiko Yamaguchi, Takahide Ikeda
A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates. IEEE J. Solid State Circuits 29 (11) (1994)
Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. IEEE J. Solid State Circuits 29 (4) (1994)