Masumi Saitoh

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 9

Top Topics

Field Effect Transistors

Comprehensive Analysis

Top Venues

Microelectron. J.

Publications

Harumi Seki, Reika Ichihara, Yusuke Higashi, Yasushi Nakasaki, Masumi Saitoh, Masamichi Suzuki
Comprehensive Analysis of Hole-Trapping in SiN Films with a Wide Range of Time Constants Based on Dynamic C-V. IRPS (2023)
Takamasa Hamai, Kunifumi Suzuki, Reika Ichihara, Yusuke Higashi, Yoko Yoshimura, Kiwamu Sakuma, Kensuke Ota, Kota Takahashi, Kazuhiro Matsuo, Shosuke Fujii, Masumi Saitoh
Novel Operation Scheme for Suppressing Disturb in HfO2-based FeFET Considering Charge- Trapping-Coupled Polarization Dynamics. IRPS (2023)
Marina Yamaguchi, Shosuke Fujii, Kensuke Ota, Masumi Saitoh
Breakdown Lifetime Analysis of HfO2-based Ferroelectric Tunnel Junction (FTJ) Memory for In-Memory Reinforcement Learning. IRPS (2020)
Shosuke Fujii, Reika Ichihara, Takuya Konno, Marina Yamaguchi, Harumi Seki, Hiroki Tanaka, Dandan Zhao, Yoko Yoshimura, Masumi Saitoh, Masato Koyama
Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication. VLSI Circuits (2019)
Yoko Yoshimura, Kensuke Ota, Masumi Saitoh
Hot carrier degradation, TDDB, and 1/f noise in Poly-Si Tri-gate nanowire transistor. IRPS (2018)
Masumi Saitoh, Shosuke Fujii, Minoru Oda, Marina Yamaguchi, Shoichi Kabuyanagi, Yoko Yoshimura, Kensuke Ota, Kiwamu Sakuma, Yuuichi Kamimuta
Emerging Non-Volatile Memory and Thin-Film Transistor Technologies for Future 3D-LSI. ESSDERC (2018)
Marina Yamaguchi, Shosuke Fujii, Yuuichi Kamimuta, Shoichi Kabuyanagi, Tsunehiro Ino, Yasushi Nakasaki, Riichiro Takaishi, Reika Ichihara, Masumi Saitoh
Impact of specific failure mechanisms on endurance improvement for HfO2-based ferroelectric tunnel junction memory. IRPS (2018)
Chika Tanaka, Masumi Saitoh, Kensuke Ota, Takayuki Ishikawa, Toshinori Numata
BSIM4 parameter extraction for tri-gate Si nanowire transistors. Microelectron. J. 47 (2016)
Chika Tanaka, Keiji Ikeda, Masumi Saitoh
New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. ESSDERC (2015)
Toshiro Hiramoto, Masumi Saitoh, Gen Tsutsui
Emerging nanoscale silicon devices taking advantage of nanostructure physics. IBM J. Res. Dev. 50 (4-5) (2006)