New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering.
Chika TanakaKeiji IkedaMasumi SaitohPublished in: ESSDERC (2015)
Keyphrases
- design methodology
- logic circuits
- power dissipation
- low power
- design process
- power consumption
- chip design
- low cost
- design criteria
- fuzzy neural network
- design methodologies
- functional decomposition
- high speed
- physical design
- tunnel diode
- design procedure
- formal specification
- artificial intelligence
- image processing
- databases
- multistage
- software engineering
- object oriented
- fuzzy logic
- database systems
- real world