Ralph K. Cavin III

Publication Activity (10 Years)

Years Active: 1977-2018
Publications (10 Years): 1

Top Topics

Emerging Technologies

Ubiquitous Learning

Top Venues

Publications

Rafic Z. Makki, Victor V. Zhirnov, Ralph K. Cavin III, Sami Issa, Marco Iansiti
Nurturing the Growth of a National Infrastructure in Emerging Technologies. Proc. IEEE 106 (7) (2018)
Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov
Science and Engineering Beyond Moore's Law. Proc. IEEE 100 (Centennial-Issue) (2012)
Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov
Prolog to the Section on Science and Engineering Beyond Moore's Law. Proc. IEEE 100 (Centennial-Issue) (2012)
George Bourianoff, Michel Brillouët, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida
Nanoelectronics Research for Beyond CMOS Information Processing. Proc. IEEE 98 (12) (2010)
Kerry Bernstein, Ralph K. Cavin III, Wolfgang Porod, Alan C. Seabaugh, Jeff Welser
Device and Architecture Outlook for Beyond CMOS Switches. Proc. IEEE 98 (12) (2010)
Michel Brillouët, George Bourianoff, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida
Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps. Proc. IEEE 98 (12) (2010)
Victor V. Zhirnov, Ralph K. Cavin III, Stephan Menzel, Eike Linn, Sebastian Schmelzer, Dennis Bräuhaus, Christina Schindler, Rainer Waser
Memory Devices: Energy-Space-Time Tradeoffs. Proc. IEEE 98 (12) (2010)
Victor V. Zhirnov, Ralph K. Cavin III
Scaling beyond CMOS: Turing-Heisenberg Rapproachment. ESSCIRC (2009)
Victor V. Zhirnov, Ralph K. Cavin III, Greg Leeming, Kosmas Galatsis
An Assessment of Integrated Digital Cellular Automata Architectures. Computer 41 (1) (2008)
George Bourianoff, Joe E. Brewer, Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov
Boolean Logic and Alternative Information-Processing Devices. Computer 41 (5) (2008)
James A. Hutchby, Ralph K. Cavin III, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff
Emerging Nanoscale Memory and Logic Devices: A Critical Assessment. Computer 41 (5) (2008)
Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff
Emerging Research Architectures. Computer 41 (5) (2008)
Victor V. Zhirnov, Greg Leeming, Kosmas Galatsis, Ralph K. Cavin III
The Viability of Cellular Automata Architectures for General Purpose Computing. ERSA (2008)
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards
A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling. IEEE J. Solid State Circuits 41 (2) (2006)
Ralph K. Cavin III, Victor V. Zhirnov
Future devices for information processing. ESSCIRC (2005)
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. IEEE Trans. Very Large Scale Integr. Syst. 12 (8) (2004)
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
Low-power design methodology for an on-chip bus with adaptive bandwidth capability. DAC (2003)
Victor V. Zhirnov, Ralph K. Cavin III, James A. Hutchby, George Bourianoff
Limits to binary logic switch scaling - a gedanken model. Proc. IEEE 91 (11) (2003)
Ralph K. Cavin III, William H. Joyner Jr., Virginia C. Wiggins
A semiconductor industry perspective on future directions in ECE education. IEEE Trans. Educ. 46 (4) (2003)
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
Accurate delay model and experimental verification for current/voltage mode on-chip interconnects. ISCAS (5) (2003)
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
Current-mode signaling in deep submicrometer global interconnects. IEEE Trans. Very Large Scale Integr. Syst. 11 (3) (2003)
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
Delay and power model for current-mode signaling in deep submicron global interconnects. CICC (2002)
Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III
Integrated parametric timing optimization of digital systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (4) (2000)
Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon, Ralph K. Cavin III
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews. J. VLSI Signal Process. 16 (2-3) (1997)
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III
The delay vernier pattern generation technique. IEEE J. Solid State Circuits 32 (4) (1997)
Jin-Ku Kang, Wentai Liu, Ralph K. Cavin III
A CMOS high-speed data recovery circuit using the matched delay sampling technique. IEEE J. Solid State Circuits 32 (10) (1997)
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III
High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique. ISCAS (1995)
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation. ARVLSI (1995)
Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray
Concurrent timing optimization of latch-based digital systems. ICCD (1995)
C. Thomas Gray, Wentai Liu, Wilhelmus A. M. Van Noije, Thomas A. Hughes, Ralph K. Cavin III
A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution. IEEE J. Solid State Circuits 29 (3) (1994)
C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
Timing constraints for wave-pipelined systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (8) (1994)
Wentai Liu, C. Thomas Gray, David Fan, William J. Farlow, Thomas A. Hughes, Ralph K. Cavin III
A 250-MHz wave pipelined adder in 2-μm CMOS. IEEE J. Solid State Circuits 29 (9) (1994)
C. Thomas Gray, Wentai Liu, Ralph K. Cavin III, Hong-Yean Hsieh
Circuit delay calculation considering data dependent delays. Integr. 17 (1) (1994)
Wentai Liu, Su-Shing Chen, Ralph K. Cavin III
A bit-serial VLSI architecture for generating moments in real-time. IEEE Trans. Syst. Man Cybern. 23 (2) (1993)
C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III
Theoretical and Practical Issues in CMOS Wave Pipelining. VLSI (1991)
Ralph K. Cavin III, Jeffrey L. Hilbert
Design of integrated circuits: directions and challenges. Proc. IEEE 78 (2) (1990)
C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III
The design of a high-performance scalable architecture for image processing applications. ASAP (1990)
C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III, Su-Shing Chen
A: a partitionable parallel/pipeline architecture for real-time image processing. ICPR (2) (1990)
Ralph K. Cavin III, Larry W. Sumney, Robert M. Burger
The Semiconductor Research Corporation: Cooperative research. Proc. IEEE 77 (9) (1989)
Wentai Liu, Thomas H. Hildebrandt, Ralph K. Cavin III
Hamiltonian Cycles in the Shuffle-Exchange Network. IEEE Trans. Computers 38 (5) (1989)
Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III
Bit-level concurrency in real-time geometric feature extractions. CVPR (1988)
Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III
Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions. ISCA (1988)
Wentai Liu, Ralph K. Cavin III
Rasterization theory, architectures, and implementations for a class of two-dimensional problems. Integr. 6 (2) (1988)
William C. Holton, Ralph K. Cavin III
A perspective on CMOS technology trends. Proc. IEEE 74 (12) (1986)
Ralph K. Cavin III
Introduction to the SRC design sciences program. DAC (1984)
Robert M. Burger, Ralph K. Cavin III, William C. Holton, Larry W. Sumney
The Impact of ICs on Computer Technology. Computer 17 (10) (1984)
Ralph K. Cavin III, Noel R. Strader
Microelectronic architectures and devices for signal and symbol processing. Integr. 1 (4) (1983)
Stephen K. Jones, Ralph K. Cavin III, William M. Reed
Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processes. IEEE Trans. Inf. Theory 28 (2) (1982)
Stephen K. Jones, Ralph K. Cavin III, Donald A. Johnston
An Efficient Computational Procedure for the Evaluation of the M/M/I Transient State Occupancy Probabilities. IEEE Trans. Commun. 28 (12) (1980)
Ralph K. Cavin III, S. C. Tandon
Distributed parameter system optimum control design via finite element discretization. Autom. 13 (6) (1977)
Stephen K. Jones, Ralph K. Cavin III
Dynamic Modeling and Control of Digital Communication Networks. Computer 10 (11) (1977)
Stephen K. Jones, Ralph K. Cavin III, J. N. Holyoak
On the Maximum Average Throughput Rate for a Tandem Node Network. IEEE Trans. Commun. 25 (10) (1977)