Low-power design methodology for an on-chip bus with adaptive bandwidth capability.
Rizwan BashirullahWentai LiuRalph K. Cavin IIIPublished in: DAC (2003)
Keyphrases
- low power
- design methodology
- high speed
- low cost
- single chip
- physical design
- power dissipation
- cmos technology
- low power consumption
- power consumption
- mixed signal
- energy dissipation
- chip design
- fuzzy neural network
- design process
- image sensor
- object oriented
- signal processor
- nm technology
- real time
- digital signal processing
- logic circuits
- ultra low power
- embedded systems
- signal processing
- fuzzy sets
- artificial neural networks
- neural network